Chargement…
Chargement…
Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
22
Done
0
Questions
96
Setup, hold, slack, critical path, timing constraints.
Zynq architecture, PS-PL communication over AXI, embedded design.
SAR ADC, R-2R DAC, comparator and digital sequencing.
ARM AMBA memory-mapped bus: 5 channels, bursts, IDs, VALID/READY handshake.
Simplified AXI variant: single-beat transactions, no bursts, ideal for register access.
AXI streaming variant: single channel, no address, for DSP / video.
PS, PL, Zynq families and hardware-software partitioning.
Block Design, addresses, validation and XSA export.
Platform, BSP, xparameters and GPIO drivers.
APU, RPU, OCM, TCM, DDR and cache coherency.
AXI ports, control, DMA, clocks, resets and interrupts.
Platform, domain, BSP and driver levels.
Source, GIC, ISR and latency.
Buffers, cache coherence and ELF sections.
BootROM, FSBL, U-Boot and BOOT.BIN.
ILA, software debugger and cross-trigger.
Registers, packaging and driver.
Kernel, Device Tree, GPIO and DMA.
Agents, transactions and protocol verification.
Platform, BSP, build and execution on the board.