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Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
7
Done
0
Questions
40
Setup, hold, slack, critical path, timing constraints.
Zynq architecture, PS-PL communication over AXI, embedded design.
SAR ADC, R-2R DAC, comparator and digital sequencing.
ARM AMBA memory-mapped bus: 5 channels, bursts, IDs, VALID/READY handshake.
Simplified AXI variant: single-beat transactions, no bursts, ideal for register access.
AXI streaming variant: single channel, no address, for DSP / video.