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Short chapter quizzes with maximum XP on the first try and detailed feedback after the correct answer.
Quizzes
15
Done
0
Questions
87
Testbench structure, clock generation, stimuli, assertions.
Moore vs Mealy, state encoding, one- or two-process style.
std_logic_1164, numeric_std, std.env, textio and practical simulation functions.
Width parameters, generic map, for generate and conditional generation.
Packages, package body, functions, procedures and shared types.
'length, 'range, 'high, 'low, 'event and synthesis attributes.
Synthesis, mapping, place, route and bitstream.
Visual IP assembly, VHDL packaging, SoC integration.
Latency, throughput, critical path, registers and temporal verification.
PISO/SIPO registers, synchronous counters, modulo counters and terminal-count signals.
Parity, syndrome, Hamming and correction limits.
Synchronous serial bus: MOSI, MISO, SCLK, CS, modes 0-3.
Two-wire open-drain serial bus, 7-bit addressing, ACK, start and stop.
Open-source SoC bus: master/slave, cycles, handshake.
Intel/Altera bus family: Avalon-MM, Avalon-ST.