I2C addressing, ACK/NACK, START/STOP conditions and VHDL FSM structure.
I2C connects components through SDA for data and SCL for clock. Open-drain outputs pull the lines low; pull-up resistors restore a high level when devices release them.
Signal
Type
Description
SDA
Bidirectional open-drain
Serial Data
SCL
Bidirectional open-drain
Serial Clock
Address and frame the exchange
Slaves use 7-bit or 10-bit addresses. Assign distinct addresses to communicate separately with multiple devices on one bus.
SDA stays stable while SCL is high, except for two conditions: START pulls SDA low and STOP lets it rise. Data changes occur while SCL is low.
A typical write using a seven-bit address follows this sequence:
The master generates START, sends the address MSB first and follows it with R/W: 0 for writing, 1 for reading. The destination acknowledges the address, and each data byte is followed by ACK or NACK. The master releases the bus with STOP.
On the ninth clock pulse, the receiver produces ACK by pulling SDA low or NACK by leaving it high. NACK may indicate refusal or the end of a read: after its final received byte, the master sends NACK to request no more data.
Build the controller
This VHDL interface exposes the command, address and bidirectional lines:
library ieee;use ieee.std_logic_1164.all;entity i2c_master is generic ( g_SYS_CLK_HZ : positive := 100_000_000; -- 100 MHz g_I2C_CLK_HZ : positive := 400_000 -- 400 kHz (Fast mode) ); port ( i_clk : in std_logic; i_rst : in std_logic; i_start : in std_logic; i_rw : in std_logic; -- '0'=write, '1'=read i_addr : in std_logic_vector(6 downto 0); i_data : in std_logic_vector(7 downto 0); o_data : out std_logic_vector(7 downto 0); o_busy : out std_logic; o_ack_err : out std_logic; io_sda : inout std_logic; io_scl : inout std_logic );end entity i2c_master;
A write FSM can follow IDLE → START → ADDR → ACK_ADDR → DATA → ACK_DATA → STOP. The interface alone is not a complete implementation; the corresponding exercise develops its behavior.
A slave can stretch the clock by holding SCL low. The master must read the line and wait for it to rise. This requires open-drain control and SCL readback on the master side too.
With multiple masters, each compares SDA with the value it intends to transmit. A master that releases the line for 1 but reads 0 loses arbitration and stops transmitting. The other continues.
Choose the speed and check the board
Mode
Maximum SCL frequency
Standard Mode
100 kHz
Fast Mode
400 kHz
Fast Mode Plus
1 MHz
High Speed Mode
3.4 MHz
Pull-ups, bus capacitance and rise times must meet the selected mode's requirements. The capacitance limit is not one universal value for every variant.
Advantages
Disadvantages
Only 2 wires
Slower than SPI
Native multi-master
Open-drain requires pull-up resistors
Addressing - no SS_N
More complex protocol
ACK/NACK for verification
Capacitance limit depends on the mode and specification