Wishbone Bus Protocol: Signals, ACK, Pipelining, and VHDL
By Dangremont JaysonAbout the author (in French)
Learn the Wishbone bus protocol, its master-slave signals and ACK handshake, pipelined transfers, VHDL implementation, and differences from AXI.
Wishbone connects a master to registers or memory with relatively few signals. The open specification published by OpenCores describes synchronous single and block transfers, plus pipelining in revision B4.
Identify requests and completion
The suffixes _I and are relative to the block. A slave's therefore connects to the master's .