Wishbone Bus Protocol: Signals, ACK, Pipelining, and VHDL

Learn the Wishbone bus protocol, its master-slave signals and ACK handshake, pipelined transfers, VHDL implementation, and differences from AXI.

What is Wishbone?

Wishbone is an open-source system bus developed by Silicore Corporation and standardized by the OpenCores Foundation. It is widely used in open-hardware designs (OpenCores, LiteX, OpenRISC) as an internal SoC bus.

Key characteristics:

• Open-source: free specification
• Simple: few signals, easy to implement
• Flexible: supports single, burst, and pipelined transfers
• Synchronous: all transactions occur on clock edges

Wishbone Signals

Signals are prefixed _i (input) or _o (output) from the master's perspective.

Read and Write Cycles

Fundamental rule: until ACK is received, the master holds STB, CYC, ADR, and WE stable.

VHDL Implementation

A typical Wishbone slave contains a register array accessible for read/write operations. The logic is simple: when CYC and STB are active, the slave decodes the address, performs the read or write, then asserts ACK to complete the transaction.

Wishbone concepts are practiced through the protocol quizzes and exercises, including slave and master implementation work.

Pipeline Mode (Wishbone B4)

Wishbone revision B4 adds pipeline mode: the master can issue new requests without waiting for ACK on the previous one. The STALL signal allows the slave to pause new requests.

Additional signal:
STALL_I : in std_logic  -- slave cannot accept a new request

Key Points

• CYC vs STB: CYC indicates the master "owns" the bus (no other master can access it), STB indicates an active transaction on this specific cycle. In simple designs, CYC = STB
• ACK latency: the slave can send ACK in the same cycle as STB (zero latency) or after several cycles (N cycles latency)
• SEL: each bit selects a byte lane - useful for byte and half-word accesses on a 32-bit bus

Comparison with AXI

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