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SPI signal lines, transfer modes, frames and VHDL implementation points.
SPI exchanges bits using a clock supplied by the master. The master selects the peripheral with SS_N. MOSI and MISO allow transmission and reception during the same exchange.
| Signal | Direction | Description |
|---|---|---|
| SCK | Master → Slave | Serial Clock |
| MOSI | Master → Slave |
| Master Out Slave In |
| MISO | Slave → Master | Master In Slave Out |
| SS_N | Master → Slave | Slave Select, active low |
In a common multi-slave arrangement, SCK, MOSI and MISO are shared and each slave has its own SS_N. Selection takes the place of addressing on this bus.
CPOL sets SCK idle level: low for 0, high for 1. CPHA selects sampling on the first edge for 0 or second for 1. Together they define four modes:
| Mode | CPOL | CPHA | Sampling | Description |
|---|---|---|---|---|
| 0 | 0 | 0 | SCK rising edge | SCK idle low, sample on rising |
| 1 | 0 | 1 | SCK falling edge | SCK idle low, sample on falling |
| 2 | 1 | 0 | SCK falling edge | SCK idle high, sample on falling |
| 3 | 1 | 1 | SCK rising edge | SCK idle high, sample on rising |
Beginner master exercises use mode 0; the slave exercise uses mode 1. For a real peripheral, use the mode specified in its datasheet.
The master drives SS_N low, supplies SCK pulses and releases SS_N at the end. Each SCK cycle carries one bit in each direction. MSB-first order is common, but some devices expect LSB first.
Keep selection active for the transaction required by the peripheral. Releasing it may reset a bit counter or finish a command; consult the device documentation for the exact behavior.
Frequency must meet slave limits and link delays, including the MISO return path. A CPOL/CPHA mismatch can corrupt data without an error indication.
For a slave sampled by a system clock, handle the external signals crossing into that domain. Two registers reduce a signal's metastability risk, but alone do not guarantee edge capture or SCK/MOSI timing consistency. Check frequency ratios and delays for the chosen architecture.
| Advantages | Disadvantages |
|---|---|
| Simple to implement | One SS_N pin per slave (many pins) |
| High speed (tens of MHz) | No acknowledgment (ACK) |
| Full-duplex | Limited distance |
| Flexible protocol | No native error detection |
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