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AXI-Lite: the simplified AXI variant for configuration registers and control interfaces.
AXI4-Lite gives software access to an IP's parameter, command and status registers. Transactions carry a single beat on a 32-bit or 64-bit bus, without bursts.
| Channel | Information carried | Sender |
|---|---|---|
| AW | Write address, protection | Master |
| W | Write data, byte selection | Master |
| B | Write response | Slave |
| AR | Read address, protection | Master |
| R | Read data and response | Slave |
Each channel has its own VALID / READY pair. The sender presents information with VALID and holds it until a rising edge where READY is also 1.
The sender must announce VALID without waiting for READY. The receiver may be ready in advance or wait for VALID. This asymmetry prevents both blocks from waiting on each other.
The Arm AMBA AXI and ACE specification, IHI 0022H covers AXI4-Lite and its VALID / READY rules.
The master presents ARADDR with ARVALID. After acceptance, the slave supplies RDATA and RRESP with RVALID until the RREADY handshake.
Here, the address transfers at C2. D0 is offered at C3 and accepted at C5. Between those cycles, RVALID stays asserted and RDATA retains D0.
The master sends AWADDR with AWVALID on AW and WDATA with WVALID on W. The slave must handle these receptions separately and remember whichever arrives first.
Waiting for AWREADY before asserting WVALID can block a slave that waits for data before accepting the address. Present the information without imposing that order.
Here, address acceptance occurs at C2 and data acceptance at C3. The slave can then present BRESP with BVALID; the master accepts it at C5 with BREADY.
On a 32-bit bus, the four WSTRB bits select four bytes. An IP supporting partial writes updates only selected bytes. Check its register map for allowed addresses and accesses, and examine RRESP and BRESP for the result.
In simulation, stall each channel separately. Check stable information and ensure a write response follows acceptance of both address and data.
In the custom AXI-Lite peripheral, connect the control interface, clock and reset, then check the address map with the diagram validator. For data transfers without addresses, read the AXI4-Stream chapter; its handshake does not replace AXI-Lite read and write channels.
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