Avalon-MM/Avalon-ST signals, handshakes and Platform Designer integration.
Platform Designer uses Avalon to connect IP. Avalon-MM carries register and memory accesses; Avalon-ST carries audio, video or network streams. The family also includes interrupt and clock interfaces, plus conduits for custom signals.
Separate command acceptance from read return
Signal
Direction (Master)
Description
address
Output
Address; units defined by interface properties
read
Output
Read request
write
Output
Write request
readdata
Input
Read data (slave → master)
writedata
Output
Write data (master → slave)
byteenable
Output
Active byte mask
waitrequest
Input
Slave requests a wait cycle
readdatavalid
Input
(pipeline) Read data is valid
In the basic case, with waitrequestAllowance = 0, the master holds command and address while waitrequest is high. For writes, it also holds data and active lanes.
A register slave without wait states keeps waitrequest low and supplies reads at its declared latency, which may be zero for combinational reads. For later responses, readdatavalid can signal valid data independently of accepting new commands. waitrequest controls that acceptance.
Respect byteenable when partial accesses are allowed. An IP limited to whole words must declare and enforce that restriction; ignoring a partial mask would overwrite other bytes.
Transfer a stream
Signal
Direction (Source)
Description
data
Output
Stream data
valid
Output
Data is valid
ready
Input
Sink can accept data
startofpacket
Output
First beat of a packet
endofpacket
Output
Last beat of a packet
empty
Output
Number of empty bytes in the last beat
error
Output
Error associated with the beat
With readyLatency = 0 and readyAllowance = 0, a transfer occurs at an edge where valid and ready are both 1:
This case resembles AXI-Stream handshaking. Avalon-ST properties can instead delay the effect of ready or allow transfers after it goes low. Check their values at both interfaces before applying this rule.
Start and end signals delimit packets. empty counts unused symbols in the final transfer; those symbols are bytes when each is eight bits wide.
Declare a custom IP
Criterion
Avalon-MM
AXI-Lite
Standard
Intel/Altera
ARM (AMBA)
Separate channels
No
Yes (5 channels)
Wait mechanism
waitrequest
valid/ready handshake
Native burst
Yes
No (AXI4 full)
Auto-generation
Platform Designer
Vivado IP Integrator
Typical use
Cyclone, Arria, Stratix
Zynq, UltraScale
Platform Designer generates the interconnect from declared interfaces. For custom IP, ports and properties must match the RTL. This declaration describes a word-addressed Avalon-MM interface:
Check reset polarity: platform examples use active-high reset, but the convention depends on the IP. For delayed RAM reads or calculations, declare latency and response signals correctly as well. Protocol quizzes and exercises provide practice with these accesses.