Learn AXI4-Stream handshaking and continuous data transfer with TVALID, TREADY, TLAST, and TKEEP, without address management.
AXI4-Stream connects a data producer to a consumer without addresses or read/write responses. The producer offers a word on with ; the consumer indicates availability with .
TDATA
TVALID
TREADY
Use this chapter when connecting a sample source, FIFO or processing pipeline. Beforehand, you should be able to read a rising-edge waveform and follow a clocked Verilog process. AXI4-Stream carries a flow of words; AXI4-Lite serves a different purpose, such as configuring registers.
Recognize a transfer
A word transfers at a rising edge where TVALID and TREADY are both 1. TVALID alone indicates an offer rather than reception.
D0 transfers at C2. D1 stalls at C3 and remains offered until acceptance at C4. D2 completes the packet at C5.
For a three-word packet, count accepted words rather than cycles with TVALID=1:
Rising edge
TVALID
TREADY
Offered word
Accepted?
C2
1
1
D0
Yes
C3
1
0
D1
No
C4
1
1
D1
Yes
C5
1
1
D2, TLAST=1
Yes
The receiver should collect D0, D1 and D2 exactly once, in that order. D1 and its sideband signals must remain unchanged during the pause. If the final word stalls instead, keep TLAST=1 until that word is accepted.
Hold data during a pause
With TVALID=1 and TREADY=0, retain the word, metadata and TVALID until transfer. Afterwards, offer the next word or deassert TVALID when no data is available.
The producer announces TVALID without waiting for TREADY. The consumer may remain ready or adjust TREADY to its capacity. RTL must respect the interface restrictions on combinational paths between inputs and outputs.
Last word of a packet, when the interface uses packets
TKEEP
Mask of bytes to retain
TUSER
Metadata defined by the connected blocks
When present, TLAST, TKEEP and TUSER accompany the relevant word and remain stable during a stall. Describe their use at both IP interfaces, particularly TUSER: the protocol gives it no universal meaning.
Connect the stream across clock domains
Read STA and clock domain crossings before connecting unrelated clocks. A valid/ready handshake in one domain does not make an asynchronous crossing safe.
The multi-clock AXI4-Stream pipeline uses a Clock Converter between 100 MHz and 150 MHz domains, followed by a Data FIFO. Build the stream path and assign each clock and reset to its own domain, then run the exercise's connection checks. Those checks validate the diagram; they do not simulate packet traffic. In a hardware testbench, also introduce backpressure and compare the accepted word sequence with the table above.