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Write self-checking VHDL testbenches with a DUT, clock, reset, stimuli, assertions, and verification before synthesis.
A testbench drives the DUT (device under test) and compares outputs with expected results. Assertions provide a verdict; waveforms help explain failures.
The testbench shown here is self-contained, with no entity ports:
entity tb_mux4to1 is
-- No ports!
endIt declares signals, instantiates the DUT and applies stimuli:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity tb_mux4to1 is
end entity tb_mux4to1;
architecture tb of tb_mux4to1 is
-- Simulation constants
constant c_CLK_PERIOD : time := 10 ns; -- 100 MHz
-- Signals to connect to the DUT
signal w_d0, w_d1, w_d2, w_d3 : std_logic := '0';
signal w_sel : std_logic_vector(1 downto 0) := "00";
signal w_y : std_logic;
begin
-- DUT instantiation
DUT : entity work.mux4to1
port map (
i_d0 => w_d0,
i_d1 => w_d1,
i_d2 => w_d2,
i_d3 => w_d3,
i_sel => w_sel,
o_y => w_y
);
-- Stimuli process
p_stimuli : process
begin
-- Test 1: select d0
w_d0 <= '1'; w_d1 <= '0'; w_d2 <= '0'; w_d3 <= '0';
w_sel <= "00";
wait for 20 ns;
assert w_y = '1' report "FAIL: sel=00 should output d0=1" severity error;
-- Test 2: select d1
w_sel <= "01";
wait for 20 ns;
assert w_y = '0' report "FAIL: sel=01 should output d1=0" severity error;
-- Test 3: select d3
w_d3 <= '1';
w_sel <= "11";
wait for 20 ns;
assert w_y = '1' report "FAIL: sel=11 should output d3=1" severity error;
report "All tests passed!" severity note;
wait; -- end simulation
end process p_stimuli;
end architecture tb;For a synchronous circuit, use one of the following clock-generation methods. Initialize the clock signal for the concurrent form:
-- Clock generation process
p_clk : process
begin
i_clk <= '0';
wait for c_CLK_PERIOD / 2;
i_clk <= '1';
wait for c_CLK_PERIOD / 2;
end process p_clk;
-- Concurrent alternative
i_clk <= not i_clk after c_CLK_PERIOD / 2;A counter test checks reset, counting and wraparound:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use std.env.all;
entity tb_counter is
end entity tb_counter;
architecture tb of tb_counter is
constant c_CLK_PERIOD : time := 10 ns;
signal i_clk : std_logic := '0';
signal i_rst : std_logic := '1';
signal o_cnt : std_logic_vector(3 downto 0);
begin
-- Clock generation
i_clk <= not i_clk after c_CLK_PERIOD / 2;
-- DUT
DUT : entity work.counter_4bit
port map (
i_clk => i_clk,
i_rst => i_rst,
o_cnt => o_cnt
);
-- Stimuli
p_test : process
begin
-- Reset active for 3 cycles
i_rst <= '1';
wait for 3 * c_CLK_PERIOD;
assert unsigned(o_cnt) = 0 report "Reset failed" severity error;
-- Start counting
i_rst <= '0';
wait for 5 * c_CLK_PERIOD;
assert unsigned(o_cnt) = 5 report "Counting incorrect" severity error;
-- Wait for overflow (16 total cycles = back to 0)
wait for 11 * c_CLK_PERIOD;
assert unsigned(o_cnt) = 0 report "Overflow incorrect" severity error;
report "Testbench completed successfully" severity note;
finish;
end process p_test;
end architecture tb;Wait for settling before reading outputs. At a clock edge, DUT assignments may still await a delta cycle, so an immediate check can observe the previous value.
| Instruction | Usage |
|---|---|
wait for 10 ns; | Wait a fixed duration |
wait until rising_edge(i_clk); | Wait for a clock edge |
wait until i_valid = '1'; | Wait for a condition |
wait; | Suspend the current process indefinitely |
assert condition report "msg" severity level; | Verification |
Severity levels classify messages; the stopping threshold depends on simulator settings:
| Level | Message |
|---|---|
note | Information |
warning | Warning |
error | Check failure |
failure | Severe failure; usual default stopping threshold |
Name checks and cover boundaries, state transitions, minimum and maximum values. Separate stimuli from expected rules where that improves the scenario.
To avoid repeated assertions, declare a local procedure before the architecture's begin:
-- Before the begin of the tb architecture
procedure check_slv(
constant i_name : in string;
constant i_observed : in std_logic_vector;
constant i_expected : in std_logic_vector
) is
begin
assert i_observed = i_expected
report i_name
& " expected=0x" & to_hstring(i_expected)
& " observed=0x" & to_hstring(i_observed)
severity error;
end procedure check_slv;Call it from the test process after settling:
wait until rising_edge(i_clk);
wait for 1 ns;
check_slv("counter after reset", o_cnt, x"0");Move shared checks into a package when several testbenches need them.
In VHDL-2008, std.env.finish explicitly ends simulation:
library STD;
use STD.ENV.ALL;
-- ...
report "Testbench completed successfully" severity note;
finish;wait; suspends only its calling process. Simulation continues if a clock remains active. For scripts or CI, finish explicitly after checks and a success message.
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