Introduction to VHDL

Name: Introduction to VHDL
Author: Dangremont Jayson

By Dangremont JaysonAbout the author (in French)

What is VHDL, its history, and why use it for FPGAs?

VHDL describes a digital circuit for simulation and, when synthesizable, implementation on an FPGA or ASIC. The description also documents architecture and helps verify behavior.

Understand the hardware model

VHDL stands for VHSIC Hardware Description Language. VHSIC (Very High Speed Integrated Circuits) was a US program in the 1980s. IEEE later standardized the language:

Year	Event
1983	Created by the DOD (US Department of Defense)
1987	First standardization IEEE 1076-1987
1993	Major revision IEEE 1076-1993 (VHDL-93)
2008	VHDL-2008: process(all) and language extensions
2019	VHDL-2019: latest current revision

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity my_circuit is
  port (
    i_a : in  std_logic;
    i_b : in  std_logic;
    o_y : out std_logic
  );
end entity my_circuit;
 
architecture rtl of my_circuit is
begin
  o_y <= i_a AND i_b;
end architecture rtl;

Criterion	VHDL	Verilog
Syntax	Verbose, strongly typed	Compact, C-like
Typing	Strict (strongly typed)	Permissive
Standard	IEEE 1076	IEEE 1364 / 1800 (SystemVerilog)