VHDL Signals vs Variables vs Constants: Key Differences

Name: VHDL Signals vs Variables vs Constants: Key Differences
Author: Dangremont Jayson

By Dangremont JaysonAbout the author (in French)

Compare VHDL signals, variables, and constants, including declaration scope, update timing, synthesis behavior, and when to use each one.

Signals, variables and constants pass values in different ways. Their choice describes model behavior; the resulting hardware depends on how they are assigned.

Property	Signal	Variable	Constant
Common use	Block connection or port	Local calculation	Fixed parameter
Assignment	Scheduled update

architecture rtl of example is
  -- Declaration in the architecture area
  signal w_intermediate : std_logic;
  signal r_counter      : unsigned(7 downto 0) := (others => '0');
begin
  -- Signal assignments are deferred
  w_intermediate <= i_a AND i_b;
  o_result       <= w_intermediate OR i_c;
end architecture rtl;

process(i_clk)
  variable v_temp : unsigned(8 downto 0);
  variable v_sum  : unsigned(7 downto 0);
begin
  if rising_edge(i_clk) then
    v_temp := unsigned('0' & i_a) + unsigned('0' & i_b);  -- immediate update
    v_sum  := v_temp(7 downto 0);                          -- v_temp already updated!
    r_result <= std_logic_vector(v_sum);
  end if;
end process;

process(i_clk)
  variable v_x : std_logic;
begin
  if rising_edge(i_clk) then
    -- With variable (immediate update)
    v_x := i_data;    -- v_x takes i_data immediately
    o_y <= v_x;       -- o_y = i_data (synchronous, same cycle)
 
    -- With signal (deferred)
    -- w_x <= i_data;
    -- o_y <= w_x;    -- o_y = old value of w_x!
  end if;
end process;

architecture rtl of uart is
  constant c_CLK_FREQ   : integer := 100_000_000;  -- 100 MHz
  constant c_BAUD_RATE  : integer := 115_200;
  constant c_DIVISOR    : integer := c_CLK_FREQ / c_BAUD_RATE;
  constant c_PREAMBLE   : std_logic_vector(7 downto 0) := x"55";
begin
  -- c_DIVISOR = 868 (computed at compile time)
end architecture rtl;

Situation	Use
Communication between processes	Signal
Intermediate value in a process	Variable
Fixed value used everywhere	Constant
Component port	Signal (port)
Synthesizable counter or register	Signal with `r_` prefix
Intermediate combinational calculation	Variable or `w_` signal

signal w_combinational : std_logic;       -- w_ = wire, unregistered
signal r_registered    : std_logic;       -- r_ = registered, flip-flop
constant c_MAX         : integer := 255;  -- c_ = constant
variable v_temp        : unsigned(7 downto 0); -- v_ = variable (internal use)

VHDL Signals vs Variables vs Constants: Key Differences

Connect blocks with signals

Calculate locally with variables

Fix parameters with constants