Overview of FPGA development tools - proprietary and open-source: Vivado, Quartus Prime, Libero SoC, and open alternatives.
The target device determines the toolchain first. It must accept the RTL, place and route resources, then produce an FPGA-compatible configuration.
This chapter helps you choose tools for an existing board or move a design to another FPGA family. You should already be able to write a and distinguish . Have the exact FPGA part number available before choosing a vendor toolchain.
The course's AMD/Xilinx examples use Vivado. Block Design connects IP, STA analyzes margins and XSIM simulates the design. ILA observes internal signals on the board. Tcl reproduces operations and automates the flow.
Available features and devices depend on edition and version:
Version and edition → check target-device, IP and feature support.Licensing → consult AMD offers for the installed version.
Check support for the device on your Nexys A7, Basys 3 or PYNQ-Z2 and for the required IP. Licensing changes over time; consult AMD's licensing page before installation.
Quartus targets Altera FPGAs. Platform Designer connects IP, often through Avalon; TimeQuest performs STA and Signal Tap supports internal debugging. Tcl scripting is also available.
Quartus Prime Lite / Standard / ProChoose the edition by supported family, part number and software version.
Check the edition required by the device and the simulator version available with your installation.
Libero targets Microchip FPGAs. SmartDesign organizes blocks and interfaces, including support for nonvolatile configuration families. Startup and reliability properties depend on the selected device.
Silver licensing covers selected devices while others require paid options; consult Microchip's matrix. Aerospace use requires an appropriate qualification process. A timing tool alone does not provide DO-254 certification for a design.
Use an open toolchain
For supported targets, including iCE40 and ECP5, a flow can combine GHDL, Yosys and nextpnr:
The flow suits scripting and CI. Check device, synthesis-backend and VHDL-construct support. Available IP libraries and graphical tools differ from vendor suites.
Identify vendor dependencies
Vivado uses XDC, while Quartus and Libero support SDC-based constraints. Supported commands are not all interchangeable:
Some attributes affect only the target synthesizer without changing simulation behavior:
-- Xilinx/Vivado onlyattribute ASYNC_REG : string;attribute ASYNC_REG of r_sync1 : signal is "TRUE";attribute KEEP : string;attribute KEEP of r_sig : signal is "TRUE"; -- prevents optimization-- Intel/Quartus onlyattribute preserve : boolean;attribute preserve of r_sig : signal is true;
Primitives also need vendor libraries and models:
-- Xilinx: BUFG, IBUF, OBUF, RAMB36E2, DSP48E2...BUFG_inst : BUFG port map (O => clk_buf, I => clk_in);-- Intel: ALTPLL, altera_std_synchronizer, ALTDPRAM...-- Microchip: GL (global buffer), MSS (hard ARM core)...
When changing families, replace or wrap these dependencies, then check RTL compatibility and synthesis results.
You have a Xilinx/AMD FPGA? → Vivado (this course)You have an Intel/Altera FPGA? → Quartus PrimeYou have a Microchip/Microsemi FPGA? → Libero SoCYou have an iCE40 or ECP5? → nextpnr + Yosys; iCEcube2 for iCE40, Diamond for ECP5You just want to simulate VHDL? → GHDL + GTKWave (subject to language support)
Check a small design before moving a whole project
Start with the guided AND gate. Its expected truth table is small enough to check in full: 00, 01 and 10 produce 0; 11 produces 1. Run the browser simulation first. This checks RTL behavior without installing a vendor toolchain.
If you have a board, synthesize the same small design for its exact part. Inspect warnings, the inferred logic and pin assignments before generating a bitstream. A combinational AND gate has no clock to constrain; for a later registered design, add the actual clock and I/O constraints and check the implemented timing report. A passing RTL simulation alone does not establish pin compatibility or timing closure.
To practice Vivado's IP workflow, use the Wishbone to AXI-Lite bridge. The exercise checks interface connections and the address map in the browser. It does not compile a bitstream or implement the bridge's RTL.