Chargement…
The fundamental distinction between combinational logic (no memory) and sequential logic (clocked).
To choose a block model, ask whether it needs to retain information. Combinational functions use current inputs; sequential functions also use stored state.
| Combinational Logic | Sequential Logic | |
|---|---|---|
| Memory | No | Yes (flip-flops) |
| Depends on past | No | Yes |
| Clock | Not needed | Used by the synchronous circuits studied here |
| Examples | Multiplexer, adder | Register, counter, FSM |
architecture rtl of mux2 is
begin
-- Concurrent assignment: immediate, combinational
o_y <= i_a when i_sel = '0' else i_b;
end architecture rtl;This logic needs no clock. Its output settles after propagation delay. FPGA synthesis implements it using resources such as LUTs and their connections.
In the synchronous sequential logic shown here, a rising or falling edge controls state updates:
architecture rtl of register_8 is
signal r_data : std_logic_vector(7 downto 0);
begin
process(i_clk)
begin
if rising_edge(i_clk) then
if i_rst = '1' then
r_data <= (others => '0');
else
r_data <= i_data;
end if;
end if;
end process;
o_data <= r_data;
end architecture rtl;The prefix r_ identifies a registered signal in these courses. D flip-flops provide storage: Q takes D's value at the active edge and retains the captured value between edges.
| Event | Q value |
|---|---|
| Rising edge | D value at the edge |
| No rising edge | Previous Q value |
process(i_clk)
begin
if rising_edge(i_clk) then
r_q <= i_d; -- simple D flip-flop
end if;
end process;Sequential logic more broadly includes circuits with state; not all sequential circuits are synchronous.
A synchronous reset takes effect at a clock edge:
process(i_clk)
begin
if rising_edge(i_clk) then
if i_rst = '1' then
r_q <= '0'; -- reset on the clock edge
else
r_q <= i_d;
end if;
end if;
end process;An asynchronous reset can act without waiting for that edge:
process(i_clk, i_rst)
begin
if i_rst = '1' then
r_q <= '0'; -- immediate reset, no clock edge required
elsif rising_edge(i_clk) then
r_q <= i_d;
end if;
end process;The choice depends on FPGA resources and circuit requirements. Synchronous reset suits many RTL blocks, but resetting every register can impede some RAM or DSP inference. For asynchronous reset, arrange synchronized deassertion in each clock domain.
A combinational process sensitivity list must include every signal read:
-- Combinational: i_a, i_b, i_sel in the list
process(i_a, i_b, i_sel)
begin
if i_sel = '0' then
w_y <= i_a;
else
w_y <= i_b;
end if;
end process;An edge-triggered process lists the clock and, where present, asynchronous reset:
-- Sequential: only i_clk
process(i_clk)
begin
if rising_edge(i_clk) then
r_q <= i_d;
end if;
end process;VHDL-2008 provides process(all) to determine sensitivity automatically. Check that the tool enables this language version.
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