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Logical, relational, arithmetic, and shift operators in VHDL.
Read a VHDL expression using both operand types and operator precedence. Parentheses make grouping explicit and prevent misinterpretation.
| Precedence | Category | Operators |
|---|---|---|
| 1, lowest | Logical | and, or, , , , |
nandnorxorxnor| 2 | Relational | =, /=, <, <=, >, >= |
| 3 | Shift and rotation | sll, srl, sla, sra, rol, ror |
| 4 | Adding | +, -, & |
| 5 | Unary sign | +, - |
| 6 | Multiplying | *, /, mod, rem |
| 7, highest | Miscellaneous | **, abs, not |
Logical operations support types including std_logic, std_logic_vector, bit and boolean. On vectors, they operate bit by bit:
-- On std_logic (1 bit)
w_y <= i_a AND i_b;
w_y <= i_a OR i_b;
w_y <= i_a XOR i_b;
w_y <= NOT i_a;
w_y <= i_a NAND i_b;
w_y <= i_a NOR i_b;
w_y <= i_a XNOR i_b;
-- On std_logic_vector (bit-by-bit)
w_mask <= w_data AND "11110000"; -- mask lower 4 bits
w_set <= w_data OR "00001111"; -- force lower 4 bits to 1Logical operators share one precedence level. The language restricts how they can be mixed; use parentheses to identify groups:
-- INCORRECT : priority ambiguity
w_y <= i_a AND i_b OR i_c; -- compile error!
-- CORRECT : parentheses required when mixing
w_y <= (i_a AND i_b) OR i_c;
w_y <= i_a AND (i_b OR i_c);A comparison returns a boolean for use in a condition:
if i_a = i_b then -- equality
if i_a /= i_b then -- not equal
if r_counter < 100 then -- strictly less than
if r_counter >= c_MAX then -- greater than or equalWith numeric_std, unsigned and signed compare as numbers. A std_logic_vector comparison is lexicographic; convert to the intended numeric type for arithmetic comparison.
numeric_std defines arithmetic on numeric vectors. Widen operands before addition to retain carry. A product's width is the sum of its operand widths:
library IEEE;
use IEEE.NUMERIC_STD.ALL;
signal r_a, r_b : unsigned(7 downto 0);
signal r_sum : unsigned(8 downto 0); -- +1 bit to avoid overflow
-- Addition and subtraction
r_sum <= ('0' & r_a) + ('0' & r_b); -- zero extension
r_a <= r_a + 1; -- increment
r_a <= r_a - r_b;
-- Multiplication (note: doubles the width)
signal r_prod : unsigned(15 downto 0);
r_prod <= r_a * r_b; -- 8 × 8 = 16 bitsDivision or modulo by a variable can require substantial logic. A fixed-modulus counter often has a simpler implementation with an explicit comparison:
if r_count = 9 then
r_count <= 0;
else
r_count <= r_count + 1;
end if;mod and rem agree for positive integers:
7 mod 4 = 3
7 rem 4 = 3For a nonzero result, A mod B takes B's sign, while A rem B takes A's sign:
(-7) mod 4 = 1
(-7) rem 4 = -3That difference matters when negative values are allowed.
The numeric_std functions shift_left, shift_right, rotate_left and rotate_right make type and direction explicit:
signal w_uns : unsigned(7 downto 0);
signal w_sig : signed(7 downto 0);
-- Logical shift (fill with '0')
w_uns <= shift_left(w_uns, 2); -- left shift by 2 (×4)
w_uns <= shift_right(w_uns, 1); -- right shift by 1 (÷2)
-- Arithmetic shift on signed: shift_right propagates the sign bit
w_sig <= shift_right(w_sig, 1);
-- Rotation
w_uns <= rotate_left(w_uns, 3);
w_uns <= rotate_right(w_uns, 3);shift_right inserts zeros on the left of an unsigned and repeats the sign bit of a signed. Operators sll, srl, sla, sra, rol and ror also exist, with their own rules and overloads.
& joins elements or vectors:
signal w_byte : std_logic_vector(7 downto 0);
signal w_hi : std_logic_vector(3 downto 0) := x"A";
signal w_lo : std_logic_vector(3 downto 0) := x"5";
signal w_bit : std_logic := '1';
w_byte <= w_hi & w_lo; -- "10100101" = 0xA5
w_byte <= w_bit & "0110011"; -- insert a bit
w_byte <= "0000" & w_lo; -- zero extensionThese operations also support masking, extension and flag checks:
-- Test a bit
if w_flags(3) = '1' then ...
-- Mask bits
w_result <= w_data AND x"0F"; -- keep lower 4 bits
-- Truncate / extend
w_16bit <= x"00" & w_8bit; -- zero-extend 8→16 bits
w_16bit <= (15 downto 8 => w_8bit(7)) & w_8bit; -- sign-extend 8→16 bits
-- Invert all bits
w_inv <= NOT w_data;
-- Count with overflow
r_counter <= r_counter + 1; -- naturally overflows to 0 (unsigned type)Check the retained width after each operation: zero extension and sign extension express different intentions.
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