Chargement…
The two fundamental blocks: the entity and the architecture.
A VHDL block has an interface, its entity, and an implementation, its architecture. This separation makes external connections visible without reading all the internal logic.
-- 1. Library declarations
The library and use clauses make libraries and package contents accessible:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- std_logic, std_logic_vector types
use IEEE.NUMERIC_STD.ALL; -- unsigned, signed, conversions| Library | Main Content |
|---|---|
IEEE.STD_LOGIC_1164 | Types std_logic, std_logic_vector |
IEEE.NUMERIC_STD | Types unsigned, signed, arithmetic operations |
STD.STANDARD | Auto-loaded - types bit, integer, boolean |
For arithmetic on signed and unsigned, use IEEE.NUMERIC_STD. Legacy packages STD_LOGIC_ARITH and STD_LOGIC_UNSIGNED are not IEEE-standard packages and can introduce ambiguous overloads.
The entity describes the component's visible ports:
entity adder is
generic (
g_WIDTH : integer := 8 -- configurable parameter
);
port (
i_clk : in std_logic;
i_rst : in std_logic;
i_a : in std_logic_vector(g_WIDTH-1 downto 0);
i_b : in std_logic_vector(g_WIDTH-1 downto 0);
o_sum : out std_logic_vector(g_WIDTH downto 0)
);
end entity adder;Each port mode determines how it is used:
| Mode | Direction | Usage |
|---|---|---|
in | Input only | Control signals, input data |
out | Output only | Results, outputs |
inout | Bidirectional | Tristate bus (rare in modern FPGA) |
buffer | Output readable internally | Avoid: prefer an internal signal |
The architecture declares internal objects before begin, followed by concurrent statements:
architecture rtl of adder is
-- Declaration area
signal w_carry : std_logic;
constant c_ZERO : std_logic_vector(g_WIDTH-1 downto 0) := (others => '0');
begin
-- Description area (all concurrent)
o_sum <= ('0' & i_a) + ('0' & i_b);
end architecture rtl;Its name is a style choice. These names are common:
| Name | Meaning |
|---|---|
rtl | Register Transfer Level (synthesizable) |
behavioral | Behavioral (sometimes simulation only) |
structural | Component instantiation |
tb | Testbench |
The following assignments describe functions operating in parallel:
architecture rtl of example is
begin
-- These three statements are all active simultaneously
o_y1 <= i_a AND i_b;
o_y2 <= i_a OR i_c;
o_y3 <= NOT i_a;
end architecture rtl;A signal assignment, instantiation or process placed directly in the architecture is concurrent. A change to i_a or i_b triggers recalculation of the affected outputs.
Line order does not establish block execution order. The process itself is concurrent; its internal statements are read in sequence to describe its behavior.
Comments begin with --:
-- Single-line comment (double dash)
-- No /* */ comments in standard VHDL
-- VHDL-2008 adds /* */ comments but few tools support them
entity my_component is -- end-of-line comment OKVHDL is case-insensitive: signal, Signal and SIGNAL denote the same keyword. Choose a consistent convention: lowercase keywords, optionally uppercase constants and generics, and prefixes distinguishing ports from signals. The coding-rules chapter explains the conventions used here.
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