Chargement…
Complete implementation of a 4-to-1 multiplexer in different VHDL styles.
A multiplexer selects an input and passes it to the output. Selection can apply to a single bit or an entire bus.
For four inputs, the two select bits give these choices:
i_sel | o_y |
|---|
"00" | i_d0 |
"01" | i_d1 |
"10" | i_d2 |
"11" | i_d3 |
A concurrent when / else assignment is compact for a few choices:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mux4to1 is
port (
i_d0 : in std_logic;
i_d1 : in std_logic;
i_d2 : in std_logic;
i_d3 : in std_logic;
i_sel : in std_logic_vector(1 downto 0);
o_y : out std_logic
);
end entity mux4to1;
architecture rtl of mux4to1 is
begin
o_y <= i_d0 when i_sel = "00" else
i_d1 when i_sel = "01" else
i_d2 when i_sel = "10" else
i_d3;
end architecture rtl;with / select presents cases as alternatives without priority:
architecture rtl of mux4to1 is
begin
with i_sel select o_y <=
i_d0 when "00",
i_d1 when "01",
i_d2 when "10",
i_d3 when others;
end architecture rtl;A process with case suits selection within a more complex block:
architecture rtl of mux4to1 is
begin
p_mux : process(i_d0, i_d1, i_d2, i_d3, i_sel)
begin
case i_sel is
when "00" => o_y <= i_d0;
when "01" => o_y <= i_d1;
when "10" => o_y <= i_d2;
when others => o_y <= i_d3;
end case;
end process p_mux;
end architecture rtl;The fallback in these examples selects i_d3. It also applies to select values containing simulation states other than 0 and 1.
The generic g_WIDTH reuses one description across widths:
entity mux4to1_bus is
generic (
g_WIDTH : integer := 8
);
port (
i_d0 : in std_logic_vector(g_WIDTH-1 downto 0);
i_d1 : in std_logic_vector(g_WIDTH-1 downto 0);
i_d2 : in std_logic_vector(g_WIDTH-1 downto 0);
i_d3 : in std_logic_vector(g_WIDTH-1 downto 0);
i_sel : in std_logic_vector(1 downto 0);
o_y : out std_logic_vector(g_WIDTH-1 downto 0)
);
end entity mux4to1_bus;
architecture rtl of mux4to1_bus is
begin
with i_sel select o_y <=
i_d0 when "00",
i_d1 when "01",
i_d2 when "10",
i_d3 when others;
end architecture rtl;Each instance fixes input and output sizes while keeping the same selection behavior.
Adding a register may help timing, at the cost of extra latency:
architecture rtl of mux4to1_reg is
signal r_out : std_logic;
begin
p_mux_reg : process(i_clk)
begin
if rising_edge(i_clk) then
if i_rst = '1' then
r_out <= '0';
else
case i_sel is
when "00" => r_out <= i_d0;
when "01" => r_out <= i_d1;
when "10" => r_out <= i_d2;
when others => r_out <= i_d3;
end case;
end if;
end if;
end process p_mux_reg;
o_y <= r_out;
end architecture rtl;Here, o_y follows the register updated at a rising edge. The testbench must account for the capture cycle. Timing improvement depends on the whole path and needs confirmation in the report.
| Style | Advantages | Disadvantages |
|---|---|---|
when/else | Compact, readable | Implicit priority (cascade) |
with/select | No priority, clear | Single selection input |
process/case | Flexible, readable | More verbose |
For a simple selection without priority, with / select makes alternatives easy to review. Use the style that clearly expresses the required behavior.
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