Verilog Hardware → Simulation

Recreate the combinational datapath that increments a BCD value from 00 to 99.

Digital logicEmbedded

Dual-priority Encoder

Identify the two highest-priority active requests in an eight-bit vector.

Digital logicIndustry

Open-drain Bus Resolver

Model four open-drain outputs connected to a shared pull-up resistor.

I/OEmbedded

Single-digit BCD Subtractor

Subtract two decimal digits with borrow. Implement every specified decision.

MathDigital logic

Balanced Parity Tree

Compute four local parities and then global parity. Implement every specified decision.

TelecomDigital logic

Symmetric Window Detector

Verilog

Compare an absolute difference against a tolerance. Implement every specified decision.

Complete Balanced Parity Tree

End-around-carry Adder

Verilog

Feed carry-out back into the sixteen-bit sum. Implement every specified decision.

Complete Symmetric Window Detector

One-hot Grant Encoder

Verilog

Turn eight requests into a one-hot grant. Implement every specified decision.

Complete End-around-carry Adder

Binary-to-Gray Datapath

Verilog

Convert a binary word into Gray code. Implement every specified decision.

Complete One-hot Grant Encoder

Intermediate

0/9

Three-request Round-robin Arbiter

Implement the three-master cyclic arbiter shown by the state diagram.

IndustryProcessor

Blackjack Dealer FSM

Recreate the state machine that requests cards until reaching at least 17.

Digital logicConsumer

Digital Alarm-clock Controller

Recreate the hour/minute registers and alarm trigger logic.

EmbeddedConsumer

PS/2 Frame Datapath

Extract and validate a PS/2 byte. Implement every specified decision.

I/OEmbedded

Programmable Divider Phase

Compute the next phase and toggle event. Implement every specified decision.

ClockingSensors

SRAM Read-cycle Decoder

Verilog

Derive CE, OE, and ready from phase. Implement every specified decision.

Complete Programmable Divider Phase

Modulo-60 Time Datapath

Verilog

Increment seconds and minutes with carry. Implement every specified decision.

Complete SRAM Read-cycle Decoder

LFSR Byte Whitener

Verilog

Advance the PRBS and XOR its low byte. Implement every specified decision.

Complete Modulo-60 Time Datapath

Blackjack Hand Datapath

Verilog

Score four cards and adjust aces. Implement every specified decision.

Complete LFSR Byte Whitener

Advanced

0/9

Pulse-mode Asynchronous Sequencer

Recreate a pulse-mode machine in which each event pulse triggers one atomic transition.

IndustryControl

Wait-state Bus Master

Recreate the master that holds a transaction until the slave is ready.

ProcessorI/O

VeSPA Pipeline Hazard Unit

Recreate the comparators and forwarding multiplexers of a processor pipeline.

ProcessorFPGA

Strided DMA Address Generator

Compute base plus index times a stride. Implement every specified decision.

MemoryProcessor

Direct-mapped Cache Tag Lookup

Split tag, index, and offset, then validate a hit. Implement every specified decision.

MemoryProcessor

DRAM Row-column Multiplexer

Verilog

Alternately present row and column. Implement every specified decision.

Complete Direct-mapped Cache Tag Lookup

PLL Lock-window Filter

Verilog

Update a counter according to phase error. Implement every specified decision.

Complete DRAM Row-column Multiplexer

VeSPA Branch Flush Control

Verilog

Choose next PC and flush commands. Implement every specified decision.

Complete PLL Lock-window Filter

BIST Signature Analyzer

Verilog

Mix a response into a polynomial signature. Implement every specified decision.