Hardware → Simulation

Wire the provided components into a structural TOP_LEVEL.

N-bit Comparator

Implement a parametric comparator capable of comparing two unsigned values.

Double Flip-Flop Synchronizer

Implement a two-stage synchronizer to safely transfer an asynchronous signal into a clock domain.

TelecomAerospace

Rising Edge Detector

Implement a rising edge detector that generates a one-clock-cycle pulse on each 0→1 transition of the input signal.

Falling Edge Detector

Implement a falling edge detector that generates a one-clock-cycle pulse on each 1→0 transition of the input signal.

4:1 Mux from 2:1 Muxes

VHDL

Build a 4-to-1 multiplexer by instantiating three 2-to-1 multiplexers from the package.

Complete Falling Edge Detector

2-to-4 Decoder

VHDL

Implement a 2-to-4 binary decoder with active-high one-hot output.

Complete 4:1 Mux from 2:1 Muxes

4-to-2 Priority Encoder

VHDL

Implement a 4-to-2 priority encoder: the binary output gives the index of the highest active bit in `i_d`.

Complete 2-to-4 Decoder

Half Subtractor

VHDL

Implement a 1-bit half subtractor producing the difference and the outgoing borrow.

Complete 4-to-2 Priority Encoder

8-bit Parity Detector (XOR Tree)

VHDL

Compute the even parity of an 8-bit word using a 3-level XOR tree.

Complete Half Subtractor

4-bit Ripple-Carry Adder

VHDL

Build a 4-bit adder by chaining four 1-bit full-adders provided in the package.

Complete 8-bit Parity Detector (XOR Tree)

D Flip-flop with Async Set/Reset

VHDL

Implement a D flip-flop with asynchronous set and reset, both priority over the clock.

Complete 4-bit Ripple-Carry Adder

T Flip-flop from D Flip-flop

VHDL

Build a T flip-flop by wiring a D flip-flop with an XOR gate.

Complete D Flip-flop with Async Set/Reset

3-bit Asynchronous (Ripple) Counter

VHDL

Build a 3-bit ripple counter by chaining three T flip-flops from the package.

Complete T Flip-flop from D Flip-flop

Divide-by-4 Frequency Divider

VHDL

Cascade two T flip-flops to produce a clock four times slower than `i_clk`.

Complete 3-bit Asynchronous (Ripple) Counter

Serial-to-Parallel Converter

VHDL

Code a parameterized shift register using a `generate` structure.

Complete Divide-by-4 Frequency Divider

Intermediate

0/10

CRC-8 Generator

Implement a CRC-8 generator (polynomial 0x07: x⁸+x²+x+1) processing one bit per clock cycle.

TelecomSecurity

Vending Machine (Moore FSM)

Implement the FSM of a vending machine accepting 3 tokens then dispensing a drink on button press.

4-digit Code Lock (Moore FSM)

Implement an FSM that unlocks if sequence `1, 2, 3, 4` is entered correctly.

3-floor Elevator (Moore FSM)

Implement the FSM of a 3-floor elevator moving toward the target floor.

Round-Robin Arbiter 2 masters (FSM)

Implement a round-robin arbiter between two masters: priority swaps after each grant.

4-phase Handshake Master (FSM)

VHDL

Implement the master FSM of a 4-phase handshake protocol (req/ack).

Complete Round-Robin Arbiter 2 masters (FSM)

Automatic Door with Safety (FSM)

VHDL

Implement the FSM of an automatic door with obstacle sensor and end-of-travel sensors.

Complete 4-phase Handshake Master (FSM)

Sequence Detector "1101" (Moore vs Mealy)

VHDL

Implement the same sequence detector in two flavours: Moore and Mealy machines.

Complete Automatic Door with Safety (FSM)

4x4 Matrix Keypad (Scan FSM)

VHDL

Implement the sequential scan of a 4x4 matrix keypad and identify the pressed key.

Complete Sequence Detector "1101" (Moore vs Mealy)

Tree Reduced XOR

VHDL

Describe a parameterized reduced XOR as a tree for a power-of-two width.

Complete 4x4 Matrix Keypad (Scan FSM)

Advanced

0/5

mu0 - Top-level assembly

Wire the mu0 processor components to build a functional top level.

Processor

UART - Top-level assembly

Wire the top-level of a full UART (TX + RX) from the provided components.

TelecomIndustry

Repeated-Addition Multiplier

Rebuild an FSMD that multiplies two 8-bit operands using repeated additions.

IndustryTelecom

GCD by Subtractions

Recode a GCD FSMD based on comparisons, swap and subtraction.

AerospaceIndustry

Square-Root Approximation

Rebuild an FSMD that approximates the magnitude of two signed 8-bit values.

TelecomIndustry