Zynq Architecture
Understand the split between the Processing System and programmable logic in Zynq-7000 and Zynq UltraScale+ MPSoC devices.
A processor and an FPGA in one device
A Zynq is a system on chip, or SoC. It combines a complete processor system and an FPGA fabric in one component. AMD calls these two parts the Processing System, or PS, and the Programmable Logic, or PL.
The PS contains ARM processors, memory controllers and peripherals. It runs software written in C or C++. The PL contains LUTs, flip-flops, block memories and DSP blocks. A LUT implements a small logic function. A flip-flop stores one bit on a clock edge. A DSP block performs arithmetic operations efficiently. Together, these resources implement circuits described in VHDL or Verilog.
This split guides the engineering work. Software handles decisions, complex protocols and the operating system. Programmable logic handles parallel data flows, custom interfaces and functions that need predictable latency.
The Zynq-7000 family
Zynq-7000 combines one or two ARM Cortex-A9 cores with a 7 series FPGA fabric. The PS contains the following resources.
| Resource | Function |
|---|---|
| APU | Runs the application and can host an operating system |
| L1 and L2 caches | Reduce the average access time for instructions and data |
| OCM | Provides 256 KiB of fast internal memory |
| DDR controller | Connects the PS to external dynamic memory |
| GIC | Prioritizes and distributes interrupts |
| PS DMA | Moves data without making the processor copy every word |
| MIO and EMIO | Connect PS peripherals to pins or to the PL |
Integrated peripherals include UART, SPI, I2C, CAN, USB, Ethernet, GPIO and SDIO. These hard peripherals avoid rebuilding standard functions in the PL.
The PL provides the hardware resources. It can implement a processing pipeline, a custom controller, an accelerator or an AXI peripheral. The PS and PL communicate mainly through AXI interfaces.
The Zynq UltraScale+ MPSoC family
Zynq UltraScale+ MPSoC keeps the PS and PL split but provides a more capable PS.
| Block | Main function |
|---|---|
| Cortex-A53 APU | 64-bit application processing and Linux |
| Cortex-R5 RPU | Deterministic real-time processing |
| PMU | Platform and power management |
| CSU | Configuration, secure boot and cryptographic functions |
| Mali GPU | Graphics processing |
| DDR controller | Access to supported DDR or LPDDR memory |
The two Cortex-R5 cores can run separate programs. They can also run in lockstep. In lockstep mode, both cores execute the same code and their results are compared. This organization is useful when fault detection matters.
MPSoC devices contain several power domains. The low-power domain contains the RPU. The full-power domain contains the APU. The PL has its own domain. The platform can therefore disable unused functions without shutting down the complete device.
Choosing between PS and PL
The choice is not based only on average speed. It also depends on latency, parallelism, throughput and maintenance.
| Requirement | Preferred location |
|---|---|
| User interface, files and networking | PS |
| Linux, TCP/IP and storage | PS |
| Real-time control loop | RPU or PL, depending on latency |
| Parallel sample processing | PL |
| Protocol with precise timing | PL |
| IP configuration and supervision | PS |
Consider an industrial camera. Linux can manage Ethernet, files and configuration. The PL can receive pixels and apply a pipelined filter. A DMA can write the images into DDR. The processor controls the hardware with a small register set and receives an interrupt when the image is ready.
MIO and EMIO
MIO pins belong directly to the PS. Vivado assigns integrated peripherals to these pins. A UART mapped to MIO does not pass through programmable logic.
EMIO signals pass through the PL. They can route a PS peripheral through PL pins or through extra logic. EMIO does not replace AXI. It carries the functional signals of a peripheral, such as UART or GPIO signals.
Use MIO when the board wiring matches the peripheral. Use EMIO when routing through the PL or adding logic is necessary.
Boot starts in the PS
After reset, the PS BootROM runs first. It reads the boot mode and loads a first program from QSPI, SD, NAND or another interface supported by the device.
The PL does not need to be configured before the PS starts. The first loader can configure the PL, initialize DDR and launch the next application.
Design method
A Zynq design usually follows these steps.
- Split the application into software and hardware functions.
- Configure the PS and PL in Vivado.
- Define addresses, clocks, resets and interrupts.
- Export the hardware platform.
- Create a software platform and application in Vitis.
- Test software and hardware together.
The complete system must be consistent. A correct hardware block can still fail if its address, clock, reset or cache policy does not match the software.
Official references
The Zynq-7000 Technical Reference Manual UG585 documents the Zynq-7000 PS. The Zynq UltraScale+ Device Technical Reference Manual UG1085 covers MPSoC domains, processors and interfaces.
Key points
The PS runs software. The PL implements parallel circuits. Zynq-7000 uses Cortex-A9 processors. Zynq UltraScale+ MPSoC adds Cortex-A53 and Cortex-R5 processors. MIO connects PS peripherals directly to pins. EMIO routes them through the PL. AXI carries transactions between system blocks.
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