Chargement…
Understand the split between the Processing System and programmable logic in Zynq-7000 and Zynq UltraScale+ MPSoC devices.
A Zynq combines a processing system, the PS, and programmable logic, the PL. Software runs on PS processors; RTL describes PL circuits.
Zynq-7000 combines one or two Cortex-A9 cores, depending on the device, with 7-series FPGA logic:
| Resource | Function |
|---|---|
| APU | Runs the application and can host an operating system |
| L1 and L2 caches | Reduce the average access time for instructions and data |
| OCM | Provides 256 KiB of fast internal memory |
| DDR controller | Connects the PS to external dynamic memory |
| GIC | Prioritizes and distributes interrupts |
| PS DMA | Moves data without making the processor copy every word |
| MIO and EMIO | Connect PS peripherals to pins or to the PL |
The PS provides peripherals including UART, SPI, I2C, CAN, USB, Ethernet, GPIO, and SDIO. The PL supplies LUTs, flip-flops, memories, and DSPs for custom interfaces, parallel processing, and accelerators. Memory-mapped exchanges use interfaces such as AXI.
Zynq UltraScale+ MPSoC expands the PS with resources that depend on the variant:
| Block | Main function |
|---|---|
| Cortex-A53 APU | 64-bit application processing and Linux |
| Cortex-R5 RPU | Deterministic real-time processing |
| PMU | Platform and power management |
| CSU | Configuration, secure boot and cryptographic functions |
| Mali GPU | Graphics processing |
| DDR controller | Access to supported DDR or LPDDR memory |
Cortex-R5 cores can run separate programs in split mode or the same program in lockstep. Lockstep compares results to detect divergence; it does not double computational throughput.
Power domains separate the low-power RPU domain, full-power APU domain, and PL. Disabling functions requires appropriate handling of dependencies and wake-up behavior.
| Requirement | Preferred location |
|---|---|
| User interface, files and networking | PS |
| Linux, TCP/IP and storage | PS |
| Real-time control loop | RPU or PL, depending on latency |
| Parallel sample processing | PL |
| Protocol with precise timing | PL |
| IP configuration and supervision | PS |
Choose according to latency, throughput, parallelism, and maintenance rather than average speed alone. In a camera, Linux can manage files, networking, and configuration while the PL receives and filters pixels through a pipeline. DMA moves images into DDR; registers and interrupts coordinate software.
MIO connects a PS peripheral directly to dedicated PS pins. EMIO routes its signals through the PL to PL pins or internal adaptation logic. A MIO UART therefore does not pass through programmable logic.
EMIO carries peripheral signals, not AXI transactions. The choice follows board wiring and routing needs.
The PS BootROM reads boot mode and loads the first stage from a source supported by the device and configuration, such as SD or QSPI. Available sources differ between generations.
The PS can boot before PL configuration. Boot software then prepares memory and configures the PL when required before starting the application. A soft processor within an FPGA would depend on that logic being configured first.
Define the PS/PL split first. Configure blocks, addresses, clocks, resets, and interrupts in Vivado; export hardware; then create the Vitis platform and application. Check both together: an incorrect address or cache policy can make otherwise correct IP unusable.
Architecture references are UG585 for Zynq-7000 and UG1085 for Zynq UltraScale+ MPSoC.
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