Interrupts and the GIC

An interrupt lets a peripheral request service. An exception can also arise from processor execution, such as an illegal access. The vector table routes execution to the relevant handlers.

Follow the request to the ISR

The peripheral sets status and asserts its request if locally enabled. The GIC checks enable, priority, and target processor. The general handler dispatches the registered ISR, which services and acknowledges the source before returning.

Enabling the GIC alone is insufficient: local source and processor exceptions must also be enabled.

Initialize and connect

XScuGic looks up configuration, initializes the instance, and connects the processor handler:

XScuGic gic;
 
int gic_init(void)
{
    XScuGic_Config *config;
    int status;
 
    config = XScuGic_LookupConfig(XPAR_SCUGIC_SINGLE_DEVICE_ID);
    if (config == NULL) {
        return XST_FAILURE;
    }
 
    status = XScuGic_CfgInitialize(&gic, config, config->CpuBaseAddress);
    if (status != XST_SUCCESS) {
        return status;
    }
 
    Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_IRQ_INT, (Xil_ExceptionHandler)XScuGic_InterruptHandler, &gic);
    Xil_ExceptionEnable();
    return XST_SUCCESS;
}

This flow uses historical BSP device-ID symbols. Adapt parameters to generated headers when the platform uses another flow.

For interval-mode TTC, calculate prescaler and interval from its clock. The handler reads and clears causes, then records the event:

static volatile u8 update_flag;
 
static void tick_handler(void *reference)
{
    XTtcPs *timer = (XTtcPs *)reference;
    u32 status = XTtcPs_GetInterruptStatus(timer);
 
    XTtcPs_ClearInterruptStatus(timer, status);
    if ((status & XTTCPS_IXR_INTERVAL_MASK) != 0U) {
        update_flag = 1U;
    }
}

int status = XScuGic_Connect(&gic, XPAR_XTTCPS_0_INTR,
                           (Xil_InterruptHandler)tick_handler, &timer);
if (status != XST_SUCCESS) {
    return status;
}
 
XScuGic_Enable(&gic, XPAR_XTTCPS_0_INTR);
XTtcPs_EnableInterrupts(&timer, XTTCPS_IXR_INTERVAL_MASK);

Complete setup must also initialize TTC, set interval, choose GIC trigger type, and start the timer. Check connection status before enabling the source.

Acknowledge at the right level

A level request remains active until its cause clears. Missing acknowledgement can immediately invoke the ISR again. An edge source needs a compatible pulse and synchronization path; trigger configuration must match hardware.

The GIC handles private and shared interrupts. GIC acknowledgement does not necessarily acknowledge the peripheral itself.

Control latency and shared data

Latency includes masking, arbitration, handler entry, and memory/cache access. DDR-resident handlers may suffer expensive initial accesses. OCM placement or cache optimization must suit the target and be measured.

Keep ISRs short: acknowledge and record events, then calculate and print elsewhere. volatile exposes flag changes but does not make a read/clear sequence atomic. A flag merges multiple ticks; lossless counting needs an appropriate counter and critical-section strategy.

Diagnose silent or repeated interrupts

Check peripheral status and mask, generated ID, GIC connection and enable, then global enable. Repeated invocation requires checking acknowledgement and edge/level mode.

The SCU GIC documentation and initialization example describe the API.

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