PS and PL Interface with AXI

Select AXI ports between the Processing System and programmable logic, then manage clocks, resets, interrupts and memory coherency.

Two separate paths

A Zynq architecture often separates the control path from the data path.

AXI is a family of communication protocols used inside the chip. AXI-Lite carries simple register reads and writes. AXI-Stream carries a continuous sequence of data without a memory address for every item.

The control path carries little data. The processor writes parameters, starts an IP and reads its status. AXI-Lite fits this requirement.

The data path carries buffers or a continuous stream. A buffer is a reserved memory area that temporarily holds data. This path uses an AXI master in the PL, a DMA and a port to PS memory.

This split avoids using the processor to copy every word. Software supervises the operation. Hardware moves and processes data.

Read a port name

The M_AXI or S_AXI prefix is written from the viewpoint of the block that owns the port.

An M_AXI_GP0 port on the PS is a master port. The PS starts transactions toward a PL peripheral.

An S_AXI_HP0 port on the PS is a slave port. A master in the PL uses it to reach DDR or another PS resource.

The drawing direction does not define the master. The block that starts a transaction is the master. The block that answers it is the slave. The block that owns the port defines the prefix.

Zynq-7000 ports

GP ports suit control transactions. HP ports suit data transfers. ACP gives an accelerator access to the cache hierarchy but requires correct memory attributes.

Zynq UltraScale+ MPSoC ports

Names change, but roles remain similar.

Choose the port from throughput, width, coherency and power-domain requirements. A wider port cannot fix an architecture that sends very small blocks or waits for the processor between transfers.

Interconnect and conversion

AXI is a point-to-point connection. In the Block Design, the engineer connects several masters and slaves through an interconnect. Connection automation can insert and configure this block after the user confirms the operation.

SmartConnect or AXI Interconnect can perform several operations.

1. Arbitration between masters.
2. Address decoding.
3. Data-width conversion.
4. AXI3 and AXI4 conversion.
5. Clock-domain crossing.
6. Register or FIFO insertion.

Automatic conversion is useful but adds latency and resources. Review the Block Design to identify inserted blocks.

Example IP control

An AXI-Lite IP can expose four registers.

#include "xil_io.h"
 
#define CONTROL_OFFSET 0x00U
#define STATUS_OFFSET  0x04U
#define LENGTH_OFFSET  0x08U
#define START_MASK     0x01U
#define DONE_MASK      0x01U
 
void accelerator_run(UINTPTR base, u32 length)
{
    Xil_Out32(base + LENGTH_OFFSET, length);
    Xil_Out32(base + CONTROL_OFFSET, START_MASK);
 
    while ((Xil_In32(base + STATUS_OFFSET) & DONE_MASK) == 0U) {
    }
}

Polling is enough for a test. A complete application often uses an interrupt so the processor can do other work.

Clocks and resets

The PS can provide several clocks to the PL. On Zynq-7000, FCLK_CLK signals often clock AXI IP. Related reset signals are also available.

Different clocks do not necessarily have a guaranteed phase relationship. Data crossing between domains needs a suitable CDC circuit. A bus connection alone is not sufficient.

Reset must be synchronized in each clock domain. Processor System Reset converts an external or PS reset into signals for interconnects and peripherals.

Interrupts from PL to PS

A PL IP can send an interrupt to the PS GIC. Several sources are often grouped with Concat before they enter the PS.

Software configures four items.

1. The interrupt source in the peripheral.
2. The interrupt identifier from xparameters.h.
3. The GIC and handler function.
4. Source acknowledgement in the peripheral.

If software does not acknowledge the source, the interrupt can trigger again immediately.

DMA and coherency

AXI DMA can read a DDR buffer, send data over AXI-Stream and write results into another buffer. The processor does not copy every element.

Correct operation depends on three points.

1. The DMA port can access the selected addresses.
2. Transfer sizes and alignment meet DMA requirements.
3. Processor caches are maintained or the selected path is coherent.

A completed DMA transfer does not always mean that the processor already sees new data. Cache policy is part of the hardware and software interface.

Official references

PS to PL and PL to PS ports are detailed in UG585 for Zynq-7000 and UG1085 for Zynq UltraScale+ MPSoC. DMA software examples are available in the official embeddedsw documentation.

Key points

Port names use the PS viewpoint. PS master ports control PL peripherals. PS slave ports accept transactions from PL masters. Control usually uses AXI-Lite. Data uses DMA and a high-performance port. Clocks, resets, interrupts and caches are part of the design.

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