PS and PL Interface with AXI
By Dangremont JaysonAbout the author (in French)
Select AXI ports between the Processing System and programmable logic, then manage clocks, resets, interrupts and memory coherency.
Chargement…
Chargement…
Select AXI ports between the Processing System and programmable logic, then manage clocks, resets, interrupts and memory coherency.
Separate control and data paths. Processor-controlled registers suit AXI-Lite. Buffers use memory-mapped AXI, while AXI-Stream carries words without per-transfer addresses.
M_AXI identifies a master port that initiates transactions. S_AXI identifies a slave port receiving requests. Drawing direction does not define the role.
On Zynq-7000, M_AXI_GP0 lets the PS access PL; S_AXI_HP0 lets a PL master reach PS resources:
| Port | Transaction direction | Common use |
|---|---|---|
M_AXI_GP0 and M_AXI_GP1 | PS to PL | AXI-Lite IP registers |
S_AXI_GP0 and S_AXI_GP1 | PL to PS | General access from a PL master |
S_AXI_HP0 to S_AXI_HP3 | PL to PS | High-throughput access to DDR or OCM |
S_AXI_ACP | PL to PS caches | Coherent accelerator access |
GP ports often serve control, HP ports serve buffers, and ACP supports cache-related coherent access with appropriate attributes.
MPSoC uses other port families:
| Port family | Use |
|---|---|
| HPM | PS access to PL peripherals |
| HP | Non-coherent PL access to the PS and DDR |
| HPC | PL access with I/O coherency support |
| LPD to PL | Low-power domain access to the PL |
| PL to LPD | PL master access to low-power domain resources |
Choose by width, throughput, coherency, and power domain. Wide ports do not compensate for tiny transfers separated by software delays.
AXI defines point-to-point interfaces. SmartConnect or AXI Interconnect connects masters and slaves, arbitrates, and decodes addresses. Configuration may also adapt width, AXI version, clock domain, or registered paths.
Inspect blocks inserted by automation: adaptations cost resources and latency. AXI3 and AXI4 differences cannot simply be ignored.
| Offset | Register | Purpose |
|---|---|---|
0x00 | CONTROL | Start bit |
0x04 | STATUS | Done and error bits |
0x08 | LENGTH | Number of elements |
0x0C | RESULT | Simple result or counter |
#include "xil_io.h"
#define CONTROL_OFFSET 0x00U
#define STATUS_OFFSET 0x04U
#define LENGTH_OFFSET 0x08U
#define START_MASK 0x01U
#define DONE_MASK 0x01U
void accelerator_run(UINTPTR base, u32 length)
{
Xil_Out32(base + LENGTH_OFFSET, length);
Xil_Out32(base + CONTROL_OFFSET, START_MASK);
while ((Xil_In32(base + STATUS_OFFSET) & DONE_MASK) == 0U) {
}
}This fragment assumes the IP clears or rearms completion on every start and finishes without error. Robust operation needs defined acknowledgement, error checks, and bounded waiting. An interrupt frees the processor during calculation.
The PS supplies PL clocks, including FCLK_CLK on Zynq-7000. Their phase relationship must be known; otherwise data crossing requires appropriate CDC.
Prepare resets per domain. Processor System Reset supplies resets whose release is synchronized to the associated clock.
PL IP can interrupt the GIC, with Concat combining sources. Configure local source, generated identifier, GIC, handler, and acknowledgement. An unacknowledged level interrupt can immediately retrigger.
AXI DMA can read DDR, stream data through PL processing, and write results. Check address reachability, sizes, alignment, then cache maintenance or actual coherency.
DMA completion alone does not guarantee the CPU sees fresh data. Buffer ownership and memory attributes belong in the software/hardware contract.
Use PS-to-AXI-Lite for registers and DMA with HP/HPC for large buffers. Cached-data sharing requires a coherent-port and attribute review. Completion notifications can replace repeated status polling.
Ports are documented in UG585 and UG1085; the AXI DMA driver documents software transfers.
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