APU, RPU and Memory

Understand application and real-time processors, caches, address spaces and memory resources in a Zynq system.

Two processor types

A Zynq UltraScale+ MPSoC has an APU and an RPU. They serve different requirements.

The Application Processing Unit uses Cortex-A53 cores. It targets rich applications, Linux and workloads that benefit from caches, virtual memory and multiple cores.

The Real-time Processing Unit uses two Cortex-R5 cores. It targets deterministic response, which means that execution time remains predictable, and low latency. The cores can run separately or in lockstep. In lockstep mode, both cores execute the same instructions and compare their results to detect faults.

The APU

The APU is the general-purpose high-performance processing unit in the PS. Each core has an L1 cache. The cores share an L2 cache and coherency infrastructure.

The Memory Management Unit, or MMU, translates virtual addresses into physical addresses and applies memory attributes. Linux uses it for process isolation and memory management. Bare-metal software can also configure attributes to distinguish normal memory from peripheral registers.

Peripheral registers must not behave like cached RAM. Xilinx input and output functions preserve hardware access semantics more clearly.

#include "xil_io.h"
 
u32 read_status(UINTPTR base)
{
    return Xil_In32(base + 0x04U);
}
 
void start_accelerator(UINTPTR base)
{
    Xil_Out32(base + 0x00U, 0x01U);
}

Offsets come from the IP specification. The base address comes from xparameters.h or an equivalent hardware description.

The RPU

The RPU is designed for real-time work. Each Cortex-R5 can access Tightly Coupled Memory, or TCM, with low and predictable latency. Error Correction Code, or ECC, detects and corrects supported memory errors.

The Memory Protection Unit, or MPU, protects memory regions. Unlike an MMU, it does not create a virtual address space. This simpler behavior supports deterministic execution.

Lockstep mode makes both cores run the same program. It improves fault detection but does not double computing performance. Split mode allows the cores to run different programs.

System memories

DDR provides capacity but has variable latency. Arbitration, refresh and other AXI masters affect access time. Strict real-time requirements can justify TCM, OCM or BRAM.

The memory map

Each master has a view of the address space. PS and PL peripherals appear at addresses defined by the architecture and Block Design.

Distinguish three pieces of information.

1. The address seen by the processor.
2. The address used by another master, such as a DMA.
3. Cache and protection attributes for the region.

Two blocks can access the same DDR cells through different paths and coherency policies.

Caches and DMA

A DMA reads and writes memory without processor copy instructions. The processor cache can then hold an old copy of the data.

Before a DMA reads a CPU-produced buffer, software usually cleans the related cache range. After a DMA writes a buffer, software usually invalidates the range before reading the new data.

#include "xil_cache.h"
 
Xil_DCacheFlushRange((UINTPTR)tx_buffer, tx_size);
start_dma_transfer(tx_buffer, rx_buffer, tx_size);
wait_for_dma();
Xil_DCacheInvalidateRange((UINTPTR)rx_buffer, tx_size);

The exact sequence depends on the AXI port and coherency mode. A coherent port can reduce maintenance operations, but memory attributes and buffer ownership still matter.

Interrupts and timers

The GIC receives interrupts, applies priorities and routes them to cores. A timer can create a periodic interrupt. A PL peripheral can report the end of processing.

An interrupt handler should be short. It acknowledges the source, records the event and leaves long processing to the main loop or a task.

Polling is acceptable for a short test. It consumes processor time and makes response time depend on the loop. Interrupts are better when the processor has other work.

Official references

Memory maps, caches and processors are documented in UG585 for Zynq-7000 and UG1085 for Zynq UltraScale+ MPSoC.

Key points

The APU targets applications and operating systems. The RPU targets real-time work. DDR provides capacity. OCM and TCM provide lower latency. Caches improve performance but require a clear policy when the processor shares buffers with a DMA or the PL.

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