Chargement…
Understand application and real-time processors, caches, address spaces and memory resources in a Zynq system.
The MPSoC's APU and RPU serve different needs. APU Cortex-A53 cores run rich applications; RPU Cortex-R5 cores help with workloads whose timing must be controlled.
| Property | APU | RPU |
|---|
| Processor | Cortex-A53 | Cortex-R5 |
| Main use | Applications and operating systems | Real-time and safety functions |
| Memory management | MMU and virtual memory | MPU without address translation |
| Local memory | Caches | TCM and caches |
| Redundant execution | Not the main operating mode | Lockstep mode available |
Each Cortex-A53 has L1 cache and the APU shares coherent L2. Its MMU translates virtual addresses and applies memory attributes for Linux process isolation and standalone applications.
Peripheral registers need appropriate attributes rather than normal cached-RAM treatment:
#include "xil_io.h"
u32 read_status(UINTPTR base)
{
return Xil_In32(base + 0x04U);
}
void start_accelerator(UINTPTR base)
{
Xil_Out32(base + 0x00U, 0x01U);
}Offsets come from the IP contract and the base from xparameters.h. I/O primitives do not remove the need for correct attributes and ordering.
The RPU accesses local TCMs. Its MPU protects regions without virtual translation. ECC detects and corrects some memory faults depending on error type. Split mode runs separate programs; lockstep runs the same program to detect divergence.
| Memory | Property | Common use |
|---|---|---|
| OCM | Fast and internal to the PS | Boot and low-latency data |
| TCM | Closely connected to the RPU | Real-time code and data |
| DDR | Large external capacity | Applications, Linux and buffers |
| BRAM and UltraRAM | Located in the PL | Hardware buffers and local tables |
| Cache | Transparent to the processor | Lower average access latency |
Exact PL resources, including UltraRAM availability, depend on the device. DDR provides capacity but variable latency due to arbitration, refresh, and other masters. TCM, OCM, or BRAM may better suit strict timing limits.
Identify CPU addresses, DMA addresses, and cache/protection attributes. PS-to-PL windows differ between Zynq-7000, MPSoC, and the accessing master.
Two masters can reach the same DDR through paths with different coherency properties.
On a noncoherent path, clean CPU-produced data before DMA reads it. Prepare receive storage before handing it to DMA, then invalidate after completion:
#include "xil_cache.h"
Xil_DCacheFlushRange((UINTPTR)tx_buffer, tx_size);
Xil_DCacheFlushRange((UINTPTR)rx_buffer, tx_size);
start_dma_transfer(tx_buffer, rx_buffer, tx_size);
wait_for_dma();
Xil_DCacheInvalidateRange((UINTPTR)rx_buffer, tx_size);Buffers must use aligned, dedicated cache lines without adjacent CPU-owned data. The CPU must not modify them during transfer. A dirty receive line left in cache could later overwrite DMA-written data.
A coherent path may reduce explicit maintenance when transaction settings and memory attributes are correct. Buffer ownership and required barriers still apply.
The GIC prioritizes and distributes interrupts. Timers can provide periodic events; PL IP can announce completion. Handlers acknowledge the source, record the event, and leave lengthy work to a task or main loop.
Polling can suit a short check but occupies the processor. Interrupts allow other work between events.
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