Verification with AXI VIP

Verify an AXI-Lite slave in simulation using a master agent, controlled transactions and protocol checks.

Verify before hardware

An AXI IP can synthesize and still be wrong. A response may use the wrong channel, VALID may incorrectly depend on READY, or a partial write may ignore WSTRB.

AXI Verification IP, or AXI VIP, is a simulation component. It acts as a master, slave or monitor. It generates transactions and checks protocol rules during simulation.

The testbench replaces the processor with an AXI VIP master. It writes several values to the LED controller and reads the register back.

Building the testbench

The simulation Block Design contains AXI VIP, the Device Under Test, or DUT, a clock and reset. The DUT is simply the hardware block being verified. The testbench imports generated packages and creates an agent from the VIP instance interface.

import axi_vip_pkg::*;
import design_axi_vip_0_0_pkg::*;
 
design_axi_vip_0_0_mst_t agent;
 
initial begin
  agent = new("master vip agent", DUT.design_i.axi_vip_0.inst.IF);
  agent.start_master();
end

The hierarchical path depends on Block Design names. Regeneration can change packages and generated class names.

AXI-Lite transactions

task axi_lite_write(input bit [31:0] addr,
                    input bit [31:0] data);
  axi_transaction wr;
 
  wr = agent.wr_driver.create_transaction("write");
  wr.set_write_cmd(addr, XIL_AXI_BURST_TYPE_INCR, 0, 0, xil_axi_size_t'(xil_clog2(32 / 8)));
  wr.set_data_block(data);
  agent.wr_driver.send(wr);
endtask

The scenario writes 0x4B, 0x36 and 0x98 to base address 0x44A00000, waits for the driver to become idle and then reads the register. The AXI-Lite course explains why this protocol does not use bursts.

Functional and protocol checks

A good test checks the result rather than only generating traffic.

if (leds !== 8'h98) begin
  $error("Unexpected LED value: %h", leds);
end

Minimum cases include reset values, several patterns, partial writes, reads, consecutive transactions and an unimplemented address.

The VIP checks AXI rules while the simulation runs. It can detect a violation even when the functional value appears correct. An AXI handshake completes when VALID and READY are both high on a clock edge. Data and addresses must remain stable while VALID is asserted and READY is low.

A test with READY always high misses backpressure, which occurs when the receiver temporarily lowers READY because it cannot accept a transfer. Write address and write data channels are independent, so an IP must not assume both handshakes occur in the same cycle.

Regression

An automated test should finish with a clear pass or fail status. Random tests should record their seed. Running the same suite after every IP change is called a regression test. It detects behavior that a modification accidentally breaks.

Simulation does not replace board testing. It reduces risk before synthesis and gives better visibility into protocol faults.

Official references

The Vivado guide catalog references the AXI Verification IP guide. Generated examples and packages remain the exact reference for the installed Vivado version.

Key points

AXI VIP replaces a bus partner and monitors protocol behavior. A useful test generates transactions, checks data, applies backpressure and covers errors. Functional success and AXI compliance are separate results.

Test your knowledge - Chapter quiz