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Verify an AXI-Lite slave in simulation using a master agent, controlled transactions and protocol checks.
An IP block can synthesize while violating AXI. Simulation should check exchanges, responses, partial writes, and results before board testing.
AXI VIP is simulation IP acting as master, slave, or monitor. In this testbench, the VIP master replaces the processor to control LEDs:
The simulation Block Design connects VIP, tested IP, clock, and reset. Its wrapper becomes the DUT. The bench imports generated packages and constructs an agent:
import axi_vip_pkg::*;
import design_axi_vip_0_0_pkg::*;
design_axi_vip_0_0_mst_t agent;
initial begin
agent = new("master vip agent", DUT.design_i.axi_vip_0.inst.IF);
agent.start_master();
endAdapt class and hierarchical path to actual design names. Start transactions only after clock initialization and reset release.
AXI-Lite has no multibeat bursts. This VIP service issues one write and checks its response:
task automatic axi_lite_write(input bit [31:0] addr,
input bit [31:0] data);
xil_axi_resp_t response;
agent.AXI4LITE_WRITE_BURST(addr, 3'b000, data, response);
if (response != XIL_AXI_RESP_OKAY)
$fatal(1, "Write failed at %h: response=%0d", addr, response);
endtaskThe API name includes BURST even for one AXI-Lite transfer. Check its signature in your version's packages.
The sequence writes 0x4B, 0x36, and 0x98 to illustrative base 0x44A00000. Wait for responses, then read the register or compare LEDs:
if (leds !== 8'h98) begin
$error("Unexpected LED value: %h", leds);
endA complete bench counts failures and finishes with a failing verdict. Printing $error alone does not define that termination policy.
Enable and monitor VIP protocol checks. A correct value in a favorable exchange does not prove handshake compliance.
While VALID is asserted and READY low, the sender holds validity and associated information until acceptance. Exercise waits on each channel rather than an always-ready receiver.
Write addresses and data are independent. A slave can coordinate acceptance but must not lose an earlier request or rely on both VALID signals asserting simultaneously.
Include reset, varied patterns, partial WSTRB, reads, consecutive transactions, and unsupported addresses. Define expected results, reproducible seeds where needed, and a timeout.
Simulation exposes protocol faults; the board then checks actual integration. The Vivado guides reference AXI VIP. AMD's AXI-Lite VIP note documents the tasks used here.
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