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Practical VHDL functions from std_logic_1164, numeric_std, std.env, textio and math_real.
Standard packages provide conversions, numeric operations and testing tools. Choose them for the data type and context: RTL calculation, elaboration or simulation.
Use numeric_std for vector arithmetic. Legacy packages std_logic_arith, std_logic_unsigned and std_logic_signed are not IEEE-standard packages.
std_logic_1164 defines nine-state logic types and associated functions:
| Function | Use |
|---|---|
rising_edge(i_clk) | Detect a rising clock edge |
falling_edge(i_clk) | Detect a falling edge |
Is_X(w_bus) | Detect an unknown value ('U', 'X', etc.) |
To_01(w_bus) | Map a vector back to 0/1 values |
to_hstring(w_bus) | Print a vector in hexadecimal during simulation |
Use rising_edge for a rising-edge register:
p_reg : process(i_clk)
begin
if rising_edge(i_clk) then
if i_rst = '1' then
r_count <= (others => '0');
else
r_count <= r_count + 1;
end if;
end if;
end process p_reg;It recognizes transitions between valid low and high std_logic levels, including weak levels. A simple i_clk'event and i_clk = '1' can also accept a transition from an unknown state.
In a testbench, Is_X detects unknown values before accepting a result:
assert not Is_X(o_data)
report "o_data contains an unknown value: " & to_hstring(o_data)
severity error;This checks the simulation model rather than physically measuring an X state.
| Function | Use |
|---|---|
to_unsigned(i, n) | Convert a natural integer to unsigned(n-1 downto 0) |
to_signed(i, n) | Convert a signed integer to signed(n-1 downto 0) |
to_integer(x) | Convert unsigned or signed to integer |
resize(x, n) | Adapt the width of an unsigned or signed value |
shift_left(x, n) | Shift left |
shift_right(x, n) | Shift right |
rotate_left(x, n) | Rotate left |
rotate_right(x, n) | Rotate right |
Conversions to a bus specify width explicitly:
signal r_count : unsigned(7 downto 0);
signal w_index : integer range 0 to 255;
w_index <= to_integer(r_count);
r_count <= to_unsigned(42, r_count'length);resize extends an unsigned with zeros and a signed with its sign. To retain an addition's carry, widen operands before calculating:
signal r_a : unsigned(7 downto 0);
signal r_b : unsigned(7 downto 0);
signal r_sum : unsigned(8 downto 0);
r_sum <= resize(r_a, r_sum'length) + resize(r_b, r_sum'length);Reducing width can lose information; check expected ranges.
to_hstring displays a vector in hexadecimal, keeping wide-bus messages compact:
report "data = 0x" & to_hstring(o_data) severity note;In VHDL-2008, std.env.finish explicitly ends the scenario:
library STD;
use STD.ENV.ALL;
-- end of testbench
report "Test completed" severity note;
finish;textio reads stimuli, compares results and writes logs. Hexadecimal read and write functions can handle vectors directly:
library STD;
use STD.TEXTIO.ALL;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
file f_vectors : text open read_mode is "vectors.txt";
variable v_line : line;
variable v_data : std_logic_vector(7 downto 0);
variable v_ok : boolean;
readline(f_vectors, v_line);
hread(v_line, v_data, v_ok);
assert v_ok
report "Invalid stimulus line"
severity error;Use these statements in the appropriate testbench regions with the required packages and VHDL version.
math_real includes sqrt, ceil, floor, sin, cos and uniform. It supports testbenches and elaboration-time constants; these calls on real values generally do not describe runtime hardware calculations.
uniform generates pseudo-random stimuli from two seeds:
library IEEE;
use IEEE.MATH_REAL.ALL;
variable v_seed1 : positive := 101;
variable v_seed2 : positive := 203;
variable v_rand : real;
uniform(v_seed1, v_seed2, v_rand);| Need | Typical function |
|---|---|
| Detect an edge | rising_edge |
| Convert an integer to a bus | to_unsigned, to_signed |
| Convert a numeric bus to integer | to_integer |
| Change width | resize |
| Print a bus in hexadecimal | to_hstring |
| Read a hexadecimal vector in simulation | hread |
| End a testbench | finish |
| Generate random stimuli | uniform |
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