Chargement…
Parameterize a VHDL block with generics and generate repeated or optional structures.
A generic fixes a parameter during elaboration. A generate uses such parameters to create instances or choose the blocks present in the design.
Bus width is a common parameter:
library IEEE;
use
The same RTL can produce an 8-bit, 16-bit or 32-bit counter through g_WIDTH. Each instance receives its value through generic map:
u_counter_16 : entity work.counter
generic map (
g_WIDTH => 16
)
port map (
i_clk => i_clk,
i_rst => i_rst,
i_en => i_en,
o_cnt => w_count_16
);Named association makes the choice visible without depending on parameter order. Provide reasonable defaults and use positive or natural when those bounds match the requirement.
for / generate expands a repeated structure during elaboration:
entity reg_bank is
generic (
g_WIDTH : positive := 8
);
port (
i_clk : in std_logic;
i_d : in std_logic_vector(g_WIDTH - 1 downto 0);
o_q : out std_logic_vector(g_WIDTH - 1 downto 0)
);
end entity reg_bank;
architecture rtl of reg_bank is
begin
g_bits : for i in 0 to g_WIDTH - 1 generate
p_bit : process(i_clk)
begin
if rising_edge(i_clk) then
o_q(i) <= i_d(i);
end if;
end process p_bit;
end generate g_bits;
end architecture rtl;This creates g_WIDTH registers. Repetition does not execute as a software loop in the FPGA.
if / generate selects a structure from a static condition:
entity pipeline_stage is
generic (
g_REGISTER_OUTPUT : boolean := true
);
port (
i_clk : in std_logic;
i_a : in unsigned(7 downto 0);
i_b : in unsigned(7 downto 0);
o_y : out unsigned(8 downto 0)
);
end entity pipeline_stage;
architecture rtl of pipeline_stage is
signal w_sum : unsigned(8 downto 0);
signal r_y : unsigned(8 downto 0);
begin
w_sum <= resize(i_a, w_sum'length) + resize(i_b, w_sum'length);
g_registered : if g_REGISTER_OUTPUT generate
p_reg : process(i_clk)
begin
if rising_edge(i_clk) then
r_y <= w_sum;
end if;
end process p_reg;
o_y <= r_y;
end generate g_registered;
g_comb : if not g_REGISTER_OUTPUT generate
o_y <= w_sum;
end generate g_comb;
end architecture rtl;With g_REGISTER_OUTPUT = false, only the combinational path is used; the unused register can be removed from the netlist. With true, the output is registered.
An if inside a process can instead describe runtime selection when its condition depends on signals. A constant condition may also be simplified by the tool.
VHDL-2008 generics can include types, subprograms and packages:
generic (
type t_data
);A generic type can let a FIFO store different data types. Check tool compatibility before using it.
Prefix parameters with g_ and label generate blocks to keep the hierarchy readable. For a value that changes during operation, use a signal or configuration register.
| Need | Tool |
|---|---|
| Parameterized width | generic g_WIDTH |
| Parameterized depth | generic g_DEPTH |
| Repeat N instances | for ... generate |
| Enable or remove a block | if ... generate |
| Change at runtime | signal or register, not generic |
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