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Learn how VHDL attributes make reusable, width-independent code and when to use 'range, 'length, 'high, 'low, and synthesis attributes.
An attribute reads a property of a type or object. For buses, it avoids repeating widths and bounds in calculations.
signal r_data : std_logic_vector(15 downto 0);
If r_data changes from 16 to 32 bits, c_WIDTH follows its new width.
| Attribute | Meaning |
|---|---|
'length | Number of elements |
'range | Range in the same direction as the object |
'reverse_range | Range in the opposite direction |
'high | Highest index |
'low | Lowest index |
'left | Index written on the left side of the declaration |
'right | Index written on the right side of the declaration |
For this signal:
signal r_data : std_logic_vector(7 downto 0);'length is 8, 'high is 7 and 'low is 0. 'range preserves 7 downto 0. 'left and 'right follow declaration order; they do not always equal 'high and 'low in that order.
A fixed-size loop depends on the original declaration:
for i in 0 to 7 loop
r_next(i) <= i_data(i);
end loop;Using the signal range follows its width and direction:
for i in i_data'range loop
r_next(i) <= i_data(i);
end loop;Also ensure that r_next accepts the visited indexes. The attribute adapts the loop without automatically resizing its destination.
For conversions, take the target width:
signal r_count : unsigned(7 downto 0);
signal w_vec : std_logic_vector(7 downto 0);
w_vec <= std_logic_vector(resize(r_count, w_vec'length));w_vec'length replaces a repeated size constant.
'event indicates a signal value change:
if i_clk'event and i_clk = '1' then
-- ...
end if;Use the dedicated function to express a rising edge:
if rising_edge(i_clk) then
-- ...
end if;rising_edge recognizes valid low-to-high std_logic transitions, rather than treating a change from an unknown value in the same way.
Synthesis attributes have a different role: they guide a particular tool, for example to preserve a signal:
attribute keep : string;
attribute keep of w_debug : signal is "true";Document the intended effect and check the name, value and scope supported by the tool. Inspect the synthesized result as well.
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