Useful VHDL Attributes
Use 'range, 'length, 'high, 'low and selected synthesis attributes without hardcoded widths.
Why Attributes Matter
An attribute asks a type, signal or range for information. The most useful ones avoid hardcoded sizes.
signal r_data : std_logic_vector(15 downto 0);
constant c_WIDTH : natural := r_data'length;If r_data changes from 16 to 32 bits, c_WIDTH follows automatically.
Range Attributes
| Attribute | Meaning |
|---|---|
'length | Number of elements |
'range | Range in the same direction as the object |
'reverse_range | Range in the opposite direction |
'high | Highest index |
'low | Lowest index |
'left | Index written on the left side of the declaration |
'right | Index written on the right side of the declaration |
Example:
signal r_data : std_logic_vector(7 downto 0);For this signal:
r_data'lengthis8;r_data'highis7;r_data'lowis0;r_data'rangeis7 downto 0.
Robust Loops
Instead of writing a loop tied to a fixed size:
for i in 0 to 7 loop
r_next(i) <= i_data(i);
end loop;use the signal range:
for i in i_data'range loop
r_next(i) <= i_data(i);
end loop;The code stays correct if i_data changes width or if the range direction changes.
Conversions and Sizes
Attributes are also useful for conversions.
signal r_count : unsigned(7 downto 0);
signal w_vec : std_logic_vector(7 downto 0);
w_vec <= std_logic_vector(resize(r_count, w_vec'length));Here, the target width comes from w_vec. The code does not repeat 8.
rising_edge Instead of 'event
The 'event attribute indicates that a signal changed value. You may encounter this style:
if i_clk'event and i_clk = '1' then
-- ...
end if;In modern VHDL, prefer:
if rising_edge(i_clk) then
-- ...
end if;rising_edge directly expresses the intent and handles std_logic transitions more cleanly.
Synthesis Attributes
Some attributes are interpreted by synthesis tools. They can guide the tool, but they should remain exceptional.
attribute keep : string;
attribute keep of w_debug : signal is "true";This example asks the tool to preserve an intermediate signal. Depending on the tool, the exact attribute name and accepted values can vary.
Best Practices
- Use
'lengthfor size conversions. - Use
'rangeto iterate over a bus. - Prefer
rising_edge(i_clk)over a condition based on'event. - Avoid magic numbers in bus widths.
- Document every synthesis attribute: it is often tool-dependent.
Key Point
Attributes make VHDL more robust. They let code follow the real size of signals instead of copying the same constants everywhere.
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