TESTBENCH

Verify priority rotation after each grant and the no-request case.

PriorityFairness

Testbench: 4-word synchronous FIFO

Verify FIFO order, empty, full and simultaneous operations.

FIFO EmptyFIFO Full

Testbench: Valid/ready buffer

Verify data preservation under backpressure and recovery.

ValidReady

Testbench: Two-cycle latency pipeline

Verify exact latency and ordering of multiple transactions.

LatencySequence

Testbench: Configurable 8-bit PWM

Verify duty cycle, configuration reload and boundaries.

Duty CycleReload

Testbench: Simplified UART transmitter

VHDL

Verify start bit, eight data bits and stop bit at the requested baud tick.

Complete Testbench: Configurable 8-bit PWM

Testbench: SPI mode-0 transmitter

VHDL

Verify clock edges, MSB-first order and transaction completion.

Complete Testbench: Simplified UART transmitter

Testbench: Watchdog with service pulse

VHDL

Verify timeout, service and alarm output.

Complete Testbench: SPI mode-0 transmitter

Testbench: One-shot generator

VHDL

Verify a fixed-width pulse and ignored triggers while active.

Complete Testbench: Watchdog with service pulse

Testbench: Parameterized stability filter

VHDL

Verify acceptance latency and rejection of short changes.

Complete Testbench: One-shot generator

Testbench: 1101 sequence detector

VHDL

Verify overlap, partial overlap and absence of false positives.

Complete Testbench: Parameterized stability filter

Testbench: 4-bit CRC calculator

VHDL

Verify CRC results on several words and reset between frames.

Complete Testbench: 1101 sequence detector

Testbench: 8-bit priority encoder

VHDL

Verify priority, validity and transitions between multiple requests.

Complete Testbench: 4-bit CRC calculator

Testbench: 4x8 register bank

VHDL

Verify read, write, addressing and reserved-address protection.

Complete Testbench: 8-bit priority encoder

Testbench: Synchronous reset controller

VHDL

Verify reset filtering and release after several clock edges.

Complete Testbench: 4x8 register bank

Testbench: Credit counter

VHDL

Verify consume, return, boundary saturation and simultaneous events.

Complete Testbench: Synchronous reset controller

Testbench: Packet-length checker

VHDL

Verify start, counting, early end and correct length.

Complete Testbench: Credit counter

Testbench: Baud tick generator

VHDL

Verify division, reload and the exactly periodic pulse.

Complete Testbench: Packet-length checker

Testbench: Simple dual-port memory

VHDL

Verify writes, reads and independence of both ports.

Complete Testbench: Baud tick generator

Testbench: Handshake controller

VHDL

Verify valid/ready, data hold and transaction completion.