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Choose VHDL, Verilog or SystemVerilog. The DUT is provided: build stimulus, self-checking controls and a strategy that detects realistic faults.
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AND gate testbench
VHDLWrite a self-checking testbench that covers the complete truth table of an AND gate.
2-to-1 multiplexer testbench
VHDLAutomatically verify both data paths and both selector values.
4-bit counter testbench
VHDLBuild a clock and verify asynchronous reset, enable, counting and wrap-around.
Testbench: OR gate
VHDLVerify all four rows of an OR gate truth table.
Testbench: XOR gate
VHDLVerify the truth table and both cases where exactly one input is active.
Testbench: Inverter gate
VHDLVerify that the output is inverted for both input values.
Complete Testbench: XOR gate
Testbench: NAND gate
VHDLVerify the negated product, especially the two-input-high case.
Complete Testbench: Inverter gate
Testbench: NOR gate
VHDLVerify the low output when an input is active and the high idle output.
Complete Testbench: NAND gate
Testbench: 2-to-4 decoder
VHDLVerify one-hot decoding and the enable behavior.
Complete Testbench: NOR gate
Testbench: 4-bit comparator
VHDLVerify less-than, equal and greater-than relations on representative values.
Complete Testbench: 2-to-4 decoder
Testbench: 4-bit parity generator
VHDLVerify even parity for zero, an odd value and a two-bit value.
Complete Testbench: 4-bit comparator
Testbench: Half adder
VHDLVerify sum and carry for all four input pairs.
Complete Testbench: 4-bit parity generator
Testbench: 1-bit full adder
VHDLVerify sum and carry with and without an input carry.
Complete Testbench: Half adder
Testbench: 4-bit adder
VHDLVerify carries, zero operands and addition overflow.
Complete Testbench: 1-bit full adder
Testbench: 4-bit subtractor
VHDLVerify difference and borrow for subtractions with and without borrow.
Complete Testbench: 4-bit adder
Testbench: 4-bit priority encoder
VHDLVerify most-significant-bit priority and the no-request case.
Complete Testbench: 4-bit subtractor
Testbench: 7-segment decoder
VHDLVerify digits 0, 1, 8 and an out-of-range value.
Complete Testbench: 4-bit priority encoder
Testbench: 4-bit shifter
VHDLVerify left and right shifts with discarded outgoing bits.
Complete Testbench: 7-segment decoder
Testbench: 4-bit enabled register
VHDLVerify asynchronous reset, capture and hold while enable is disabled.
Complete Testbench: 4-bit shifter
Testbench: Serial shift register
VHDLVerify serial insertion and bit progression across several edges.
Complete Testbench: 4-bit enabled register
Testbench: Rising-edge detector
VHDLVerify that a one-cycle pulse appears only on a rising transition.
Complete Testbench: Serial shift register
Testbench: Enabled D flip-flop
VHDLVerify rising-edge capture and hold when enable is low.
Complete Testbench: Rising-edge detector
Testbench: 4-bit down counter
VHDLVerify reset, hold and wrap-around from zero to fifteen.
Complete Testbench: Enabled D flip-flop
Testbench: Modulo-10 counter
VHDLVerify the decimal sequence and return to zero after nine.
Complete Testbench: 4-bit down counter
Testbench: 4-bit ring counter
VHDLVerify the active-bit rotation and cyclic return.
Complete Testbench: Modulo-10 counter
Testbench: 4-bit LFSR
VHDLVerify the pseudo-random sequence and the non-zero lock-up protection.
Complete Testbench: 4-bit ring counter
Testbench: Pulse stretcher
VHDLVerify that an input pulse produces the defined output duration.
Complete Testbench: 4-bit LFSR
Testbench: Debounce filter
VHDLVerify that an input remains stable for several cycles before acceptance.
Complete Testbench: Pulse stretcher
Testbench: 4-bit PWM
VHDLVerify duty-cycle boundaries and ramp transitions.
Complete Testbench: Debounce filter
Testbench: 4-bit timer
VHDLVerify loading, countdown and the completion pulse.
Complete Testbench: 4-bit PWM
Testbench: Traffic-light FSM
VHDLVerify cyclic state transitions and reset to the initial state.
Complete Testbench: 4-bit timer
Testbench: 101 sequence detector
VHDLVerify overlapping detection and incomplete sequences.
Complete Testbench: Traffic-light FSM
Testbench: 4-bit accumulator
VHDLVerify conditional addition, hold and modulo overflow.
Complete Testbench: 101 sequence detector
Testbench: 4-bit saturating adder
VHDLVerify saturation at fifteen instead of wrap-around.
Complete Testbench: 4-bit accumulator
Testbench: Binary-to-Gray converter
VHDLVerify zero, maximum and multi-bit transition values.
Complete Testbench: 4-bit saturating adder
Testbench: One-hot checker
VHDLVerify zero, one active position and multiple active bits.
Complete Testbench: Binary-to-Gray converter
Testbench: 5-input majority voter
VHDLVerify the four-to-one and three-to-two thresholds.
Complete Testbench: One-hot checker
Testbench: 8-bit parity generator
VHDLVerify even, odd and extreme data words.
Complete Testbench: 5-input majority voter
Testbench: Register with priority clear
VHDLVerify clear priority over writes and the hold behavior.
Complete Testbench: 8-bit parity generator
Testbench: Parameterized majority voter
VHDLVerify decisions on profiles close to the threshold.
Complete Testbench: Register with priority clear