Specification

Combine automatic and manual requests to drive three actuators without a clock.

IndustryEmbedded

8-to-3 Priority Encoder

Encode eight requests into a three-bit index with fixed priority and a validity flag.

EmbeddedIndustry

BCD-to-7-segment Decoder

Convert a BCD digit into active-high controls for a 7-segment display with priority blanking.

EmbeddedIndustry

12-bit Unsigned Adder-subtractor

Build a combinational arithmetic unit with addition overflow and subtraction underflow detection.

MathEmbedded

Dead-band Thermostat

Control a heater and cooler around a target using a five-degree dead band.

IndustryEmbedded

Three-input Boolean Circuit

Verilog

Translate a Boolean expression into a combinational network.

Complete Dead-band Thermostat

Inkjet Bus Decoder

Verilog

Decode a nozzle number into a safe one-hot command.

Complete Three-input Boolean Circuit

Fail-safe Traffic-light Decoder

Verilog

Decode a one-hot state and force red for every invalid code.

Complete Inkjet Bus Decoder

Traffic-light Enable Gate

Verilog

Add a global enable to traffic-light commands.

Complete Fail-safe Traffic-light Decoder

3-bit 2-to-1 Multiplexer

Verilog

Select one of two three-bit words.

Complete Traffic-light Enable Gate

Active-low Night Light

Verilog

Drive an active-low lamp from daylight and an active-low enable.

Complete 3-bit 2-to-1 Multiplexer

8-bit Adder with Carry

Verilog

Add two bytes and a carry-in without losing the ninth bit.

Complete Active-low Night Light

4-bit Magnitude Comparator

Verilog

Compare two unsigned numbers with three mutually exclusive flags.

Complete 8-bit Adder with Carry

Parity Generator and Checker

Verilog

Generate an even-parity bit and detect an invalid parity frame.

Complete 4-bit Magnitude Comparator

D Flip-flop with Asynchronous Reset

Verilog

Store one bit on rising edges with a priority asynchronous reset.

Complete Parity Generator and Checker

8-bit Register with Enable

Verilog

Load or retain one byte according to an enable signal.

Complete D Flip-flop with Asynchronous Reset

Serial-in Parallel-out Shift Register

Verilog

Assemble eight serially received bits into a parallel register.

Complete 8-bit Register with Enable

Ripple-carry Adder

Verilog

Build a four-bit adder from four full adders.

Complete Serial-in Parallel-out Shift Register

Adder-subtractor with Overflow

Verilog

Perform signed addition and subtraction with carry and overflow flags.

Complete Ripple-carry Adder

4-bit Unsigned Multiplier

Verilog

Compute the full product of two four-bit unsigned numbers.

Complete Adder-subtractor with Overflow

Two-digit BCD Adder

Verilog

Add two BCD numbers from 00 to 99 with a decimal carry.

Complete 4-bit Unsigned Multiplier

PAL-style Address Decoder

Verilog

Decode three memory regions and report forbidden transactions.

Complete Two-digit BCD Adder

Four-digit BCD Sanitizer

Verilog

Validate every BCD nibble and block illegal words. Implement every specified decision.

Complete PAL-style Address Decoder

Eight-bit Thermometer Decoder

Verilog

Convert a contiguous run of LSB ones into binary. Implement every specified decision.

Complete Four-digit BCD Sanitizer

Eight-bit Saturating Adder

Verilog

Add two bytes without allowing wraparound. Implement every specified decision.

Complete Eight-bit Thermometer Decoder

BCD Magnitude Comparator

Verilog

Compare two BCD numbers after validation. Implement every specified decision.

Complete Eight-bit Saturating Adder

Five-input Majority Voter

Verilog

Take a majority decision across five redundant channels. Implement every specified decision.

Complete BCD Magnitude Comparator

One-hot Vector Analyzer

Verilog

Verify that exactly one bit is active and return its index. Implement every specified decision.

Complete Five-input Majority Voter

Leading-one Detector

Verilog

Locate the most-significant active bit. Implement every specified decision.

Complete One-hot Vector Analyzer

Programmable Address Window

Verilog

Decode an address between two inclusive bounds. Implement every specified decision.

Complete Leading-one Detector

4-bit Johnson Counter

Verilog

Build a shift counter that cycles through its eight Johnson states.

Complete Programmable Address Window

Transparent Latch

Verilog

Describe a latch that is transparent while its enable is high.

Complete 4-bit Johnson Counter

Intermediate

0/38

Modulo-10 Decade Counter

Design a four-bit synchronous counter that advances from 0 through 9 and then wraps to zero.

EmbeddedIndustry

10-bit Down-counter Timer

Load a duration, decrement it every cycle, and flag zero before arithmetic wraparound.

EmbeddedReal-time

Reloading Periodic Timer

Store a period, count down to zero, and then automatically reload the programmed value.

EmbeddedReal-time

Parameterized Counter

Create a counter whose width is selected at instantiation.

Digital logicFPGA

4-bit Up-down Counter

Count in both directions with enable and modulo-sixteen wraparound.

Digital logicFPGA

Modulo-12 Counter

Verilog

Count from zero through eleven and pulse on wraparound.

Complete 4-bit Up-down Counter

Pulse Stretcher

Verilog

Turn a one-cycle pulse into an active level of a fixed duration.

Complete Modulo-12 Counter

Switch Debouncer

Verilog

Filter unstable transitions on an asynchronous input.

Complete Pulse Stretcher

16 x 8 Asynchronous-read RAM

Verilog

Model a small memory with synchronous write and combinational read.

Complete Switch Debouncer

16 x 8 Synchronous-read RAM

Verilog

Model a RAM whose read and write operations occur on rising edges.

Complete 16 x 8 Asynchronous-read RAM

Dual-read Register File

Verilog

Build an eight-register file with one write and two simultaneous reads.

Complete 16 x 8 Synchronous-read RAM

8 x 8 Synchronous FIFO

Verilog

Implement an eight-byte queue with empty and full flags.

Complete Dual-read Register File

Seven-segment Decoder ROM

Verilog

Use a combinational lookup table to display a hexadecimal digit or blank the display.

Complete 8 x 8 Synchronous FIFO

Single-digit BCD Adder

Verilog

Add two BCD decimal digits and a carry-in.

Complete Seven-segment Decoder ROM

Barrel Shifter and Rotator

Verilog

Shift or rotate a byte by zero through seven positions in one combinational cycle.

Complete Single-digit BCD Adder

1011 Sequence Detector

Verilog

Detect an overlapping serial sequence with a Mealy state machine.

Complete Barrel Shifter and Rotator

Programmable Timer

Verilog

Load a period and produce a pulse after the requested number of cycles.

Complete 1011 Sequence Detector

Hamming (7,4) Code

Verilog

Encode four bits and automatically correct one single-bit error.

Complete Programmable Timer

LFSR Stream Cipher

Verilog

Combine each byte with a reproducible pseudo-random sequence.

Complete Hamming (7,4) Code

One’s-complement Checksum

Verilog

Compute the checksum of packets made of sixteen-bit words.

Complete LFSR Stream Cipher

PS/2 Mouse Packet Decoder

Verilog

Assemble three PS/2 bytes into buttons and signed movements.

Complete One’s-complement Checksum

Blackjack Score Engine

Verilog

Compute the best value of a five-card hand without exceeding 21.

Complete PS/2 Mouse Packet Decoder

PRBS Sequence Checker

Verilog

Compute the next LFSR state and count mismatches. Implement every specified decision.

Complete Blackjack Score Engine

SRAM Byte-lane Mapper

Verilog

Merge one byte according to two byte enables. Implement every specified decision.

Complete PRBS Sequence Checker

PS/2 Frame Validator

Verilog

Check start, stop, and odd parity. Implement every specified decision.

Complete SRAM Byte-lane Mapper

Reciprocal Frequency Estimator

Verilog

Divide a reference count by a measured period. Implement every specified decision.

Complete PS/2 Frame Validator

Windowed Watchdog Decision

Verilog

Classify a kick as early, valid, or late. Implement every specified decision.

Complete Reciprocal Frequency Estimator

Eight-request Rotating Arbiter

Verilog

Select the first request after the previous winner. Implement every specified decision.

Complete Windowed Watchdog Decision

BCD Digit Multiplier

Verilog

Multiply two BCD digits and produce a two-digit BCD result.

Complete Eight-request Rotating Arbiter

BCD Decimal Divider

Verilog

Divide a two-digit BCD value by one BCD digit and return quotient and remainder.

Complete BCD Digit Multiplier

VGA Digit Character ROM

Verilog

Generate decimal-digit pixels from a character code and a position in an 8×8 cell.

Complete BCD Decimal Divider

PDM Counter Decimator

Verilog

Measure the bit density of a PDM stream over 16-sample windows.

Complete VGA Digit Character ROM

Single-Entry AXI-Stream Buffer

Verilog

Buffer one AXI-Stream byte and handle backpressure without losing data.

Complete PDM Counter Decimator

SPI Mode 0 Master

Verilog

Transmit and receive one SPI mode 0 byte with a configurable clock divider.

Complete Single-Entry AXI-Stream Buffer

Five-Tap FIR Filter

Verilog

Compute a five-tap FIR output for each valid input sample.

Complete SPI Mode 0 Master

Four-Source Interrupt Controller

Verilog

Latch four requests and report the highest-priority enabled request.

Complete Five-Tap FIR Filter

Serial CRC-16/CCITT-FALSE Calculator

Verilog

Update a CRC-16/CCITT value from an MSB-first serial stream.

Complete Four-Source Interrupt Controller

8-bit Carry-Lookahead Adder

Verilog

Add two bytes using carry lookahead grouped into four-bit blocks.

Complete Serial CRC-16/CCITT-FALSE Calculator

Advanced

0/27

Schedule the five steps of a complex product

Describe the sequence that selects operands, enables partial products, and writes the real and imaginary results.

MathDSP

Complex Multiplier Datapath

Combinationally compute the product of two signed complex numbers.

Iterative 8 x 8 Multiplier

Multiply two bytes in eight cycles using shifts and additions.

Iterative Restoring Divider

Compute an unsigned quotient and remainder in eight iterations.

8-bit ALU with Flags

Combine eight arithmetic and logic operations with status flags.

4 x 4 Matrix Keypad Scanner

Verilog

Scan four rows and encode the detected key.

Complete 8-bit ALU with Flags

8N1 UART Transmitter

Verilog

Serialize one byte with a start bit, eight data bits, and a stop bit.

Complete 4 x 4 Matrix Keypad Scanner

8N1 UART Receiver

Verilog

Sample an 8N1 serial frame and report invalid stop bits.

Complete 8N1 UART Transmitter

PS/2 Receiver

Verilog

Receive a PS/2 keyboard frame and check its start, parity, and stop bits.

Complete 8N1 UART Receiver

VGA Synchronization Generator

Verilog

Generate pixel counters, visible area, and parameterized synchronization pulses.

Complete PS/2 Receiver

Fixed-priority Bus Arbiter

Verilog

Grant a bus to one requester at a time and hold the grant until release.

Complete VGA Synchronization Generator

3 x 3 Sobel Operator

Verilog

Compute a gradient-magnitude approximation over a nine-pixel window.

Complete Fixed-priority Bus Arbiter

Asynchronous SRAM Controller

Verilog

Turn an internal request into a timed asynchronous SRAM read or write cycle.

Complete 3 x 3 Sobel Operator

Burst DMA Controller

Verilog

Copy a sequence of words between two address spaces with separate handshakes.

Complete Asynchronous SRAM Controller

Direct-mapped Cache Controller

Verilog

Cache four words and refill one line on a miss.

Complete Burst DMA Controller

Digital PLL Loop Filter

Verilog

Integrate lead and lag events from a digital phase detector.

Complete Direct-mapped Cache Controller

DRAM Refresh Decision Unit

Verilog

Arbitrate between normal access and overdue refresh. Implement every specified decision.

Complete Digital PLL Loop Filter

Fast-page DRAM Command

Verilog

Detect an open-row hit and select RAS/CAS. Implement every specified decision.

Complete DRAM Refresh Decision Unit

Urgent Memory Arbiter

Verilog

Prioritize urgent requests, then apply rotation. Implement every specified decision.

Complete Fast-page DRAM Command

Cache Write-policy Unit

Verilog

Decide hit, allocation, or write-back. Implement every specified decision.

Complete Urgent Memory Arbiter

DMA Descriptor Address

Verilog

Compute an indexed descriptor address. Implement every specified decision.

Complete Cache Write-policy Unit

Binary16 Floating-point Classifier

Verilog

Classify zero, subnormal, normal, infinity, and NaN. Implement every specified decision.

Complete DMA Descriptor Address

Parallel Register with Scan Chain

Verilog

Add a serial test-shift mode to a parameterized parallel register.

Complete Binary16 Floating-point Classifier

Logic BIST Controller

Verilog

Generate fifteen patterns from a 4-bit LFSR and compact the circuit-under-test responses.

Complete Parallel Register with Scan Chain

March Memory Test Controller

Verilog

Test a 16-byte RAM by writing and reading back two complementary patterns.

Complete Logic BIST Controller

SECDED Code for 8 Bits

Verilog

Encode eight bits with an extended Hamming code and correct a single-bit error.

Complete March Memory Test Controller

Distributed-Arithmetic FIR Filter

Verilog

Implement a four-tap signed FIR using a lookup table and serial accumulator.