TESTBENCH

Write a self-checking testbench that covers the complete truth table of an AND gate.

Truth TableOperation

2-to-1 multiplexer testbench

Automatically verify both data paths and both selector values.

SelectionData Paths

4-bit counter testbench

Build a clock and verify asynchronous reset, enable, counting and wrap-around.

ResetEnable

Testbench: OR gate

Verify all four rows of an OR gate truth table.

Truth TableOperation

Testbench: XOR gate

Verify the truth table and both cases where exactly one input is active.

Truth TableOperation

Testbench: Inverter gate

VHDL

Verify that the output is inverted for both input values.

Complete Testbench: XOR gate

Testbench: NAND gate

VHDL

Verify the negated product, especially the two-input-high case.

Complete Testbench: Inverter gate

Testbench: NOR gate

VHDL

Verify the low output when an input is active and the high idle output.

Complete Testbench: NAND gate

Testbench: 2-to-4 decoder

VHDL

Verify one-hot decoding and the enable behavior.

Complete Testbench: NOR gate

Testbench: 4-bit comparator

VHDL

Verify less-than, equal and greater-than relations on representative values.

Complete Testbench: 2-to-4 decoder

Testbench: 4-bit parity generator

VHDL

Verify even parity for zero, an odd value and a two-bit value.

Complete Testbench: 4-bit comparator

Testbench: Half adder

VHDL

Verify sum and carry for all four input pairs.

Complete Testbench: 4-bit parity generator

Testbench: 1-bit full adder

VHDL

Verify sum and carry with and without an input carry.

Complete Testbench: Half adder

Testbench: 4-bit adder

VHDL

Verify carries, zero operands and addition overflow.

Complete Testbench: 1-bit full adder

Testbench: 4-bit subtractor

VHDL

Verify difference and borrow for subtractions with and without borrow.

Complete Testbench: 4-bit adder

Testbench: 4-bit priority encoder

VHDL

Verify most-significant-bit priority and the no-request case.

Complete Testbench: 4-bit subtractor

Testbench: 7-segment decoder

VHDL

Verify digits 0, 1, 8 and an out-of-range value.

Complete Testbench: 4-bit priority encoder

Testbench: 4-bit shifter

VHDL

Verify left and right shifts with discarded outgoing bits.

Complete Testbench: 7-segment decoder

Testbench: 4-bit enabled register

VHDL

Verify asynchronous reset, capture and hold while enable is disabled.

Complete Testbench: 4-bit shifter

Testbench: Serial shift register

VHDL

Verify serial insertion and bit progression across several edges.

Complete Testbench: 4-bit enabled register

Testbench: Rising-edge detector

VHDL

Verify that a one-cycle pulse appears only on a rising transition.

Complete Testbench: Serial shift register

Testbench: Enabled D flip-flop

VHDL

Verify rising-edge capture and hold when enable is low.

Complete Testbench: Rising-edge detector

Testbench: 4-bit down counter

VHDL

Verify reset, hold and wrap-around from zero to fifteen.

Complete Testbench: Enabled D flip-flop

Testbench: Modulo-10 counter

VHDL

Verify the decimal sequence and return to zero after nine.

Complete Testbench: 4-bit down counter

Testbench: 4-bit ring counter

VHDL

Verify the active-bit rotation and cyclic return.

Complete Testbench: Modulo-10 counter

Testbench: 4-bit LFSR

VHDL

Verify the pseudo-random sequence and the non-zero lock-up protection.

Complete Testbench: 4-bit ring counter

Testbench: Pulse stretcher

VHDL

Verify that an input pulse produces the defined output duration.

Complete Testbench: 4-bit LFSR

Testbench: Debounce filter

VHDL

Verify that an input remains stable for several cycles before acceptance.

Complete Testbench: Pulse stretcher

Testbench: 4-bit PWM

VHDL

Verify duty-cycle boundaries and ramp transitions.

Complete Testbench: Debounce filter

Testbench: 4-bit timer

VHDL

Verify loading, countdown and the completion pulse.

Complete Testbench: 4-bit PWM

Testbench: Traffic-light FSM

VHDL

Verify cyclic state transitions and reset to the initial state.

Complete Testbench: 4-bit timer

Testbench: 101 sequence detector

VHDL

Verify overlapping detection and incomplete sequences.

Complete Testbench: Traffic-light FSM

Testbench: 4-bit accumulator

VHDL

Verify conditional addition, hold and modulo overflow.

Complete Testbench: 101 sequence detector

Testbench: 4-bit saturating adder

VHDL

Verify saturation at fifteen instead of wrap-around.

Complete Testbench: 4-bit accumulator

Testbench: Binary-to-Gray converter

VHDL

Verify zero, maximum and multi-bit transition values.

Complete Testbench: 4-bit saturating adder

Testbench: One-hot checker

VHDL

Verify zero, one active position and multiple active bits.

Complete Testbench: Binary-to-Gray converter

Testbench: 5-input majority voter

VHDL

Verify the four-to-one and three-to-two thresholds.

Complete Testbench: One-hot checker

Testbench: 8-bit parity generator

VHDL

Verify even, odd and extreme data words.

Complete Testbench: 5-input majority voter

Testbench: Register with priority clear

VHDL

Verify clear priority over writes and the hold behavior.

Complete Testbench: 8-bit parity generator

Testbench: Parameterized majority voter

VHDL

Verify decisions on profiles close to the threshold.

Complete Testbench: Register with priority clear

Intermediate

0/20

Testbench: 4-way round-robin arbiter

Verify priority rotation after each grant and the no-request case.

PriorityFairness

Testbench: 4-word synchronous FIFO

Verify FIFO order, empty, full and simultaneous operations.

FIFO EmptyFIFO Full

Testbench: Valid/ready buffer

Verify data preservation under backpressure and recovery.

ValidReady

Testbench: Two-cycle latency pipeline

Verify exact latency and ordering of multiple transactions.

LatencySequence

Testbench: Configurable 8-bit PWM

Verify duty cycle, configuration reload and boundaries.

Duty CycleReload

Testbench: Simplified UART transmitter

VHDL

Verify start bit, eight data bits and stop bit at the requested baud tick.

Complete Testbench: Configurable 8-bit PWM

Testbench: SPI mode-0 transmitter

VHDL

Verify clock edges, MSB-first order and transaction completion.

Complete Testbench: Simplified UART transmitter

Testbench: Watchdog with service pulse

VHDL

Verify timeout, service and alarm output.

Complete Testbench: SPI mode-0 transmitter

Testbench: One-shot generator

VHDL

Verify a fixed-width pulse and ignored triggers while active.

Complete Testbench: Watchdog with service pulse

Testbench: Parameterized stability filter

VHDL

Verify acceptance latency and rejection of short changes.

Complete Testbench: One-shot generator

Testbench: 1101 sequence detector

VHDL

Verify overlap, partial overlap and absence of false positives.

Complete Testbench: Parameterized stability filter

Testbench: 4-bit CRC calculator

VHDL

Verify CRC results on several words and reset between frames.

Complete Testbench: 1101 sequence detector

Testbench: 8-bit priority encoder

VHDL

Verify priority, validity and transitions between multiple requests.

Complete Testbench: 4-bit CRC calculator

Testbench: 4x8 register bank

VHDL

Verify read, write, addressing and reserved-address protection.

Complete Testbench: 8-bit priority encoder

Testbench: Synchronous reset controller

VHDL

Verify reset filtering and release after several clock edges.

Complete Testbench: 4x8 register bank

Testbench: Credit counter

VHDL

Verify consume, return, boundary saturation and simultaneous events.

Complete Testbench: Synchronous reset controller

Testbench: Packet-length checker

VHDL

Verify start, counting, early end and correct length.

Complete Testbench: Credit counter

Testbench: Baud tick generator

VHDL

Verify division, reload and the exactly periodic pulse.

Complete Testbench: Packet-length checker

Testbench: Simple dual-port memory

VHDL

Verify writes, reads and independence of both ports.

Complete Testbench: Baud tick generator

Testbench: Handshake controller

VHDL

Verify valid/ready, data hold and transaction completion.

Complete Testbench: Simple dual-port memory

Advanced

0/10

Testbench: Modeled asynchronous FIFO

Verify flags and data order with two independent clocks.

FIFO EmptyFIFO Full

Testbench: Streaming register slice

Verify throughput, retention under backpressure and no data loss.

ValidReady

Testbench: Fair arbiter under backpressure

Verify fairness, request preservation and removal of a blocked client.

FairnessBackpressure

Testbench: UART receiver

Verify sampling, start/stop bits and framing error reporting.

SamplingFraming Error

Testbench: SPI memory controller

Verify command-address-data sequencing and return to idle.

ProtocolLatency

Testbench: Pipelined multiplier

VHDL

Verify latency, one-transaction-per-cycle throughput and signed boundaries.

Complete Testbench: SPI memory controller

Testbench: Two-output packet router

VHDL

Verify routing, conservation and blocking when an output is full.

Complete Testbench: Pipelined multiplier

Testbench: Credit-based FIFO

VHDL

Verify throughput, credit consumption and no send without credit.

Complete Testbench: Two-output packet router

Testbench: Pulse synchronizer

VHDL

Verify that a pulse is captured once despite different clocks.

Complete Testbench: Credit-based FIFO

Testbench: Packet assembler

VHDL

Verify length, checksum, backpressure and separation of two packets.