Specification

Design a two-input NAND logic gate. This is the universal gate: any logic function can be built using NAND gates.

Design a two-input NOR logic gate. Like NAND, it is a universal gate.

Design a two-input XNOR (equivalence) logic gate. The output is active when both inputs are the same.

Design a half adder that adds two bits without carry-in.

Design a 1-bit full adder with carry-in and carry-out. This block is the fundamental building block of any arithmetic unit.

Design a purely combinational 4-to-1 multiplexer. The 2-bit selector chooses which of the 4 inputs is forwarded to the output.

Design a 2-to-4 binary decoder with an enable signal. The output is a one-hot code corresponding to the selector value when the decoder is active.

Design an 8-bit parity checker. The output indicates whether the number of 1-bits in the input is odd (parity = 1) or even (parity = 0).

Design a 4-bit combinational comparator that compares two unsigned numbers and indicates whether the first is greater than, equal to, or less than the second.

Implement a D flip-flop with enable and active-high asynchronous reset. The flip-flop stores i_d on the rising edge only if i_en is active.

Implement a 4-bit register with enable and active-high asynchronous reset.

Implement a 4-bit left shift register with serial input and asynchronous reset.

Implement a 4-bit serial-in parallel-out (SIPO) shift register with asynchronous reset. Bits enter serially and are available in parallel.

Implement a 4-bit synchronous up counter with enable and asynchronous reset.

Implement a 4-bit synchronous down counter with enable and asynchronous reset. Reset initializes to maximum value (15).

Implement a 4-bit ring counter with asynchronous reset. A single '1' bit circulates through the register.

Implement a generic SPI slave in mode 1 (CPOL=0, CPHA=1) receiving a 32-bit frame.

Implement an SPI master (mode 0: CPOL=0, CPHA=0) capable of transmitting and receiving a byte over an SPI bus.

Implement an SPI master in mode 0 (CPOL=0, CPHA=0) capable of transferring 8 bits serially.

Implement a synchronous BCD counter that counts from 0 to 9 then wraps to 0, with active-low asynchronous reset and enable input.

Implement a generic clock divider that divides the input frequency by 2 × G_HALF, with asynchronous reset.

Implement a 4-bit serial shift register (SISO) with asynchronous reset. Bits shift right on each rising edge.

Implement a Mealy state machine that detects the binary sequence "101" on a serial input, with overlap handling.

Implement a combinational ALU performing 4 operations on two 8-bit operands: addition, subtraction, AND, and OR, with carry flag.

Implement a transparent latch to understand this classic FPGA pitfall. When enable is high, output follows input; when enable is low, output holds its value.

Implement an 8-bit loadable shift register combining parallel load and left shift, with load taking priority.

Implement a pulse stretcher that extends a single-cycle signal into an output active for G_CYCLES clock cycles.

Implement a safety watchdog timer: a counter decrements continuously and triggers a timeout if no i_kick signal is received in time.

Implement a 3-state FSM controller (OFF, BLINK, ON) that drives an LED with blinking. Each button press advances the sequence.

Implement a PWM generator with a sequential counter and a combinational output controlled by the duty cycle.

Implement an 8-bit Linear Feedback Shift Register (LFSR) with seed loading and combinational feedback output.

Implement a 4-sample moving average filter with a sequential shift register and combinational average computation.

Implement an N-bit parallel register with enable and combinational update detection.

Implement a two flip-flop CDC synchronizer with combinational rising and falling edge detection.

Implement a synchronous CRC-16 calculator, bit by bit, with the CCITT polynomial and a combinational output of the CRC register.

Implement the first two phases of an I2C master: START condition and sending the 7-bit address + R/W bit via a 5-state FSM.

Implement a 7-segment decoder that converts a BCD digit (0-9) into 7 signals to light the correct display segments, with enable.

Implement a top level that instantiates a BCD counter and a 7-segment decoder, correctly wiring internal signals and external ports.

Design a 4-bit combinational multiplier that computes the product of two unsigned numbers on an 8-bit output.

Design a combinational converter that transforms an 8-bit BCD (Binary-Coded Decimal) number into its 7-bit binary value.

Design a purely combinational 8-to-1 multiplexer. The 3-bit selector chooses which of the 8 inputs is forwarded to the output.

Design a 1-to-2 demultiplexer. The input is routed to one of the two outputs based on the selector.

Design a 1-to-4 demultiplexer. The input is routed to one of the four outputs based on the 2-bit selector.

Design a 3-to-8 binary decoder with enable signal. The output is a one-hot code corresponding to the selector value.

Design a 4-bit binary to Gray code converter. Gray code is used in communications because only one bit changes between consecutive values.

Design a 4-bit Gray code to binary converter. Inverse operation of the binary to Gray converter.

Design a 4-bit combinational subtractor that computes the difference of two unsigned numbers with borrow indication.

Implement a JK flip-flop with active-high asynchronous reset. The JK flip-flop is the most versatile: it can hold, set, reset, or toggle its output.

Implement a T (Toggle) flip-flop with active-high asynchronous reset. When T='1', the output toggles on each rising edge.

Implement a synchronous SR flip-flop with active-high asynchronous reset. S sets the output to '1', R resets it to '0'.

Design a combinational encoder that converts a valid BCD digit to Excess-3 code.

Encode 4 data bits with three even-parity bits to form a Hamming (7,4) word.

Fix an incomplete combinational process that keeps an old value when `i_sel = "11"`.

Build a synchronous counter that only walks through 4-bit odd values.

Implement a down counter that reloads itself when it reaches zero.

Convert an 8-bit thermometer code to a binary count.

Design an 8-bit sequential Fibonacci sequence generator.

Reverse the order of four nibbles packed into a 16-bit word.

Add a stream of unsigned samples into a 12-bit accumulator.

Detect whether four 4-bit values contain at least one duplicate.

Compute the signed difference between two 8-bit samples.

Accumulate a packet of samples and report the sum on the last word.

Compute cumulative sums for four 4-bit values.

Count the differing bits between two 8-bit words.

Count consecutive zeros starting at the least significant bit.

Accept a frame when its destination MAC is local or broadcast.

Check that a packet length sits inside an allowed window.

Detect common VLAN TPIDs and extract the TCI field.

Implement an 8-bit signed ReLU activation.

Compute the maximum over a 2x2 window of 8-bit pixels.

Return the maximum value and its index among four inputs.

Implement an N-bit ripple carry adder using only logical operators, without any arithmetic library.

Implement a generic bidirectional counter with parallel load, enable, and asynchronous reset.

Implement a debouncer circuit with configurable stabilization time via generics.

Implement an 8-to-3 combinational priority encoder that encodes the position of the highest-priority active bit.

Implement a 4-bit Johnson counter with synchronous reset. The counter goes through a sequence of 8 states before returning to its initial state.

Implement an 8-bit barrel shifter performing a logical left shift in 3 combinational stages (shift-by-4, shift-by-2, shift-by-1).

Implement a W1C register: bits are set via i_set_en and cleared by writing 1 via i_clr_en.

Generate a 1µs periodic pulse from a system clock with known period.

Implement a generic synchronous N-bit counter with enable, asynchronous reset and overflow indication.

Implement an 8-bit combinational comparator that compares two unsigned numbers and indicates their relationship.

Implement a 4-bit combinational block selectable between addition and subtraction via a control signal.

Implement a generic cascadable comparator with cascade inputs for connecting multiple stages.

Implement an 8-bit register with parallel load enable and asynchronous reset.

Implement a 4-bit shift register that can shift left, shift right, parallel load, or hold its value.

Implement an 8-word by 4-bit read-only memory (ROM), purely combinational.

Implement a 16-word by 4-bit ROM using a VHDL constant array.

Implement an 8-word by 4-bit RAM with synchronous write and asynchronous read.

Implement a 16-word by 4-bit RAM with synchronous write and asynchronous read.

Implement an 8-deep, 8-bit LIFO stack with push, pop, and empty/full flags.

Implement an 8-word by 8-bit dual-port RAM: independent write and read ports.

Implement a 4-register, 8-bit register file with 1 write port and 2 read ports.

Implement a 4-bit Carry Lookahead Adder (CLA).

Implement an 8-bit CLA adder by cascading two 4-bit CLA blocks.

Implement a 4-bit, 2-stage barrel shifter that can logically shift left by 0 to 3 positions.

Implement an adder for a simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1.xxxx).

Implement a multiplier for the same simplified float format: 1 sign bit, 3 exponent bits (bias 3), 4 mantissa bits (implicit 1).

Implement an even parity generator: generates a parity bit for 7 data bits, and verifies an 8-bit word (7 data + 1 parity).

Implement a population counter: count the number of '1' bits in an 8-bit vector.

Implement a priority multiplexer: 4 data channels of 4 bits with request bits. The highest-priority active channel is selected.

Implement a 4-phase handshake synchronizer to transfer a data bus between two independent clock domains.

Implement a 5-tap direct-form FIR low-pass filter with line buffer and fixed coefficients.

Transform a 5x5 combinational multiplier into a 4-stage pipelined architecture.

Decode a Hamming (7,4) word, compute the syndrome and correct one single-bit error.

Implement a Parallel-In Serial-Out register with parallel load and controlled shifting.

Design a synchronous counter that cycles through states 0 to 5 with enable and terminal-count pulse.

Create a `time_of_day_pkg` package, a `record` type and a reusable time-of-day counter.

Implement a combinational arbiter that grants the bus to the requester with the lowest numeric priority.

Compare two signed-magnitude numbers without treating them as two's-complement values.

Code a bit-order reverser compatible with vectors of different sizes and directions.

Convert an 8-bit binary word into three BCD digits.

Implement a 4-bit counter that exposes its value as Gray code.

Count consecutive zeros starting at the most significant bit.

Compute the difference between two consecutive valid samples.

Linearly interpolate between four fixed table points.

Control four 4-bit counters with select, increment, and clear.

Accumulate four histogram bins from 2-bit samples.

Generate a read-then-write sequence to copy four words.

Accumulate signed values into four scratchpad locations.

Determine whether a 4-bit value is prime.

Output the maximum of the last four valid samples.

Compute `n!` for a 3-bit input from 0 to 5.

Check whether four nibbles form a palindrome sequence.

Find whether any pair among four values reaches a target.

Compress a 4-bit stream by emitting symbol and run length on changes.

Detect a local maximum in an 8-bit sample stream.

Search a target in four sorted ascending values.

Compute the dot product of two four-element 4-bit vectors.

Insert a stream of four values into an internal sorted array.

Return the most frequent value among four 4-bit values.

Detect an increasing run followed by a decreasing run in four values.

Split a 14-byte Ethernet II header into its main fields.

Compute the one’s-complement checksum over ten 16-bit IPv4 header words.

Detect an IPv4/Ethernet ARP request targeting the local address.

Implement unsigned 8x8 multiply-accumulate.

Implement 8-bit integer division in eight steps, with quotient, remainder, and divide-by-zero detection.

Measure the exact number of system cycles between two rising edges of a synchronized external signal.

Approximate a sigmoid function from a signed Q4.4 input with a 16-level lookup table.

Add four unsigned words with one adder reused over four cycles.

Compress four operands without propagating carry every cycle, then perform one final addition.

Compute an 8 by 8-bit signed product with additions and shifts over eight cycles.

Smooth large changes while passing small variations in a pixel stream.

Implement an interrupt generator: each IT vector stays active for g_MIN_WIDTH_PULSE cycles then is reported in the status register.

Implement a generic AXI4-Lite master capable of performing read and write accesses on an AXI4-Lite bus.

Implement a generic AXI4-Lite slave with simplified register interface.

Implement a simple AXI4 master managing the three write channels: Write Address (AW), Write Data (W) and Write Response (B).

Implement a 16-bit accumulator-based mini processor: ALU, PC/IR/ACC/R registers, control FSM, and top-level assembly. 14 instructions covered.

Implement a hardware SHA-256 core on a 512-bit block: logical functions, message schedule shift register, compression unit and top-level FSM.

Implement a successive-approximation conversion FSMD to drive an internal DAC and read a comparator.

Implement a simplified IEEE-754 single-precision multiplier with mantissa/exponent split.

Build a simulation ROM from Intel HEX records provided by the project.

Develop a functional µ-law compression model for a normalized real-valued signal.

Model a simple DDR output from two opposite-edge registers.

Build a decimal seconds/tenths stopwatch driven by an external tick.

Implement a small 8-bit FIFO between two clock domains.

Implement an integer IIR biquad cell with fixed coefficients.

Average four samples then output one decimated sample.

Arbitrate two masters onto a single memory port.

Sort four 4-bit values with a comparator network inspired by bubble sort.

Merge two already-sorted pairs into four sorted outputs.

Compute the median of five 4-bit values.

Implement a 3-tap 1D convolution with fixed coefficients `1,2,1`.

Transpose a 2x2 byte matrix packed into 32 bits.

Measure the longest `+1` run in four already-sorted values.

Compute one neuron with a single multiply-accumulate unit reused across several cycles.

Compute two fully connected neurons in parallel from four signed inputs.

Implement signed multiplication by recoding multiplier transitions.

Compute a sum or difference reduced to the range zero through m minus one.

Compute x times y modulo m over eight cycles without a combinational multiplier.

Compute a modular product in the Montgomery domain with eight binary iterations.

Divide two unsigned integers with eight steps alternating subtraction and addition.